12b4374cd5
Also fix and extend the current implementation: - AtomicRMWOp::Clr != AtomicRmwOp::And, as the input needs to be inverted first. - Inputs to the cmp for the RMWLoop case are sign-extended when needed. - Lower Xchg to Swp. - Lower Sub to Add with a negated input. - Added more runtests. Copyright (c) 2022, Arm Limited.
47 lines
1.5 KiB
Plaintext
47 lines
1.5 KiB
Plaintext
test run
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target s390x
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; We can't test that these instructions are right regarding atomicity, but we can
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; test if they perform their operation correctly
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function %atomic_cas_big_i16(i32, i64, i16, i16) -> i32 {
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ss0 = explicit_slot 4
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block0(v0: i32, v1: i64, v2: i16, v3: i16):
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v4 = stack_addr.i64 ss0
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store.i32 big v0, v4
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v5 = iadd.i64 v4, v1
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v6 = atomic_cas.i16 big v5, v2, v3
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v7 = load.i32 big v4
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return v7
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}
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; run: %atomic_cas_big_i16(0x12345678, 0, 0x1234, 0xabcd) == 0xabcd5678
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; run: %atomic_cas_big_i16(0x12345678, 0, 0x4321, 0xabcd) == 0x12345678
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; run: %atomic_cas_big_i16(0x12345678, 2, 0x5678, 0xabcd) == 0x1234abcd
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; run: %atomic_cas_big_i16(0x12345678, 2, 0x8765, 0xabcd) == 0x12345678
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function %atomic_cas_big_i8(i32, i64, i8, i8) -> i32 {
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ss0 = explicit_slot 4
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block0(v0: i32, v1: i64, v2: i8, v3: i8):
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v4 = stack_addr.i64 ss0
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store.i32 big v0, v4
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v5 = iadd.i64 v4, v1
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v6 = atomic_cas.i8 big v5, v2, v3
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v7 = load.i32 big v4
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return v7
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}
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; run: %atomic_cas_big_i8(0x12345678, 0, 0x12, 0xab) == 0xab345678
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; run: %atomic_cas_big_i8(0x12345678, 0, 0x21, 0xab) == 0x12345678
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; run: %atomic_cas_big_i8(0x12345678, 1, 0x34, 0xab) == 0x12ab5678
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; run: %atomic_cas_big_i8(0x12345678, 1, 0x43, 0xab) == 0x12345678
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; run: %atomic_cas_big_i8(0x12345678, 2, 0x56, 0xab) == 0x1234ab78
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; run: %atomic_cas_big_i8(0x12345678, 2, 0x65, 0xab) == 0x12345678
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; run: %atomic_cas_big_i8(0x12345678, 3, 0x78, 0xab) == 0x123456ab
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; run: %atomic_cas_big_i8(0x12345678, 3, 0x87, 0xab) == 0x12345678
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