a4a8c83aab
Add a TailRecipe.rex() method which creates an encoding recipe with a REX prefix. Define I64 encodings with REX.W for i64 operations and with/without REX for i32 ops. Only test the with-REX encodings for now. We don't yet have an instruction shrinking pass that can select the non-REX encodings.
112 lines
3.8 KiB
Python
112 lines
3.8 KiB
Python
"""
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Intel Encodings.
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"""
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from __future__ import absolute_import
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from cdsl.predicates import IsUnsignedInt
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from base import instructions as base
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from base.formats import UnaryImm
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from .defs import I32, I64
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from . import recipes as r
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for inst, opc in [
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(base.iadd, 0x01),
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(base.isub, 0x29),
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(base.band, 0x21),
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(base.bor, 0x09),
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(base.bxor, 0x31)]:
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I32.enc(inst.i32, *r.rr(opc))
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I64.enc(inst.i64, *r.rr.rex(opc, w=1))
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I64.enc(inst.i32, *r.rr.rex(opc))
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# REX-less encoding must come after REX encoding so we don't use it by
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# default. Otherwise reg-alloc would never use r8 and up.
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I64.enc(inst.i32, *r.rr(opc))
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I32.enc(base.copy.i32, *r.ur(0x89))
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I64.enc(base.copy.i64, *r.ur.rex(0x89, w=1))
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I64.enc(base.copy.i32, *r.ur.rex(0x89))
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I64.enc(base.copy.i32, *r.ur(0x89))
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# Immediate instructions with sign-extended 8-bit and 32-bit immediate.
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for inst, rrr in [
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(base.iadd_imm, 0),
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(base.band_imm, 4),
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(base.bor_imm, 1),
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(base.bxor_imm, 6)]:
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I32.enc(inst.i32, *r.rib(0x83, rrr=rrr))
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I32.enc(inst.i32, *r.rid(0x81, rrr=rrr))
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I64.enc(inst.i64, *r.rib.rex(0x83, rrr=rrr, w=1))
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I64.enc(inst.i64, *r.rid.rex(0x81, rrr=rrr, w=1))
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I64.enc(inst.i32, *r.rib.rex(0x83, rrr=rrr))
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I64.enc(inst.i32, *r.rid.rex(0x81, rrr=rrr))
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I64.enc(inst.i32, *r.rib(0x83, rrr=rrr))
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I64.enc(inst.i32, *r.rid(0x81, rrr=rrr))
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# TODO: band_imm.i64 with an unsigned 32-bit immediate can be encoded as
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# band_imm.i32. Can even use the single-byte immediate for 0xffff_ffXX masks.
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# Immediate constants.
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I32.enc(base.iconst.i32, *r.puid(0xb8))
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I64.enc(base.iconst.i32, *r.puid.rex(0xb8))
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I64.enc(base.iconst.i32, *r.puid(0xb8))
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# The 32-bit immediate movl also zero-extends to 64 bits.
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I64.enc(base.iconst.i64, *r.puid.rex(0xb8),
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instp=IsUnsignedInt(UnaryImm.imm, 32))
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I64.enc(base.iconst.i64, *r.puid(0xb8),
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instp=IsUnsignedInt(UnaryImm.imm, 32))
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# Sign-extended 32-bit immediate.
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I64.enc(base.iconst.i64, *r.uid.rex(0xc7, rrr=0, w=1))
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# Finally, the 0xb8 opcode takes an 8-byte immediate with a REX.W prefix.
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I64.enc(base.iconst.i64, *r.puiq.rex(0xb8, w=1))
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# 32-bit shifts and rotates.
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# Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit
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# and 16-bit shifts would need explicit masking.
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I32.enc(base.ishl.i32.i32, *r.rc(0xd3, rrr=4))
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I32.enc(base.ushr.i32.i32, *r.rc(0xd3, rrr=5))
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I32.enc(base.sshr.i32.i32, *r.rc(0xd3, rrr=7))
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# Loads and stores.
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I32.enc(base.store.i32.i32, *r.st(0x89))
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I32.enc(base.store.i32.i32, *r.stDisp8(0x89))
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I32.enc(base.store.i32.i32, *r.stDisp32(0x89))
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I32.enc(base.istore16.i32.i32, *r.st(0x66, 0x89))
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I32.enc(base.istore16.i32.i32, *r.stDisp8(0x66, 0x89))
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I32.enc(base.istore16.i32.i32, *r.stDisp32(0x66, 0x89))
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I32.enc(base.istore8.i32.i32, *r.st_abcd(0x88))
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I32.enc(base.istore8.i32.i32, *r.stDisp8_abcd(0x88))
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I32.enc(base.istore8.i32.i32, *r.stDisp32_abcd(0x88))
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I32.enc(base.load.i32.i32, *r.ld(0x8b))
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I32.enc(base.load.i32.i32, *r.ldDisp8(0x8b))
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I32.enc(base.load.i32.i32, *r.ldDisp32(0x8b))
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I32.enc(base.uload16.i32.i32, *r.ld(0x0f, 0xb7))
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I32.enc(base.uload16.i32.i32, *r.ldDisp8(0x0f, 0xb7))
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I32.enc(base.uload16.i32.i32, *r.ldDisp32(0x0f, 0xb7))
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I32.enc(base.sload16.i32.i32, *r.ld(0x0f, 0xbf))
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I32.enc(base.sload16.i32.i32, *r.ldDisp8(0x0f, 0xbf))
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I32.enc(base.sload16.i32.i32, *r.ldDisp32(0x0f, 0xbf))
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I32.enc(base.uload8.i32.i32, *r.ld(0x0f, 0xb6))
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I32.enc(base.uload8.i32.i32, *r.ldDisp8(0x0f, 0xb6))
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I32.enc(base.uload8.i32.i32, *r.ldDisp32(0x0f, 0xb6))
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I32.enc(base.sload8.i32.i32, *r.ld(0x0f, 0xbe))
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I32.enc(base.sload8.i32.i32, *r.ldDisp8(0x0f, 0xbe))
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I32.enc(base.sload8.i32.i32, *r.ldDisp32(0x0f, 0xbe))
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#
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# Call/return
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#
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I32.enc(base.call, *r.call_id(0xe8))
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I32.enc(base.call_indirect.i32, *r.call_r(0xff, rrr=2))
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I32.enc(base.x_return, *r.ret(0xc3))
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I64.enc(base.x_return, *r.ret(0xc3))
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