43a86f14d5
This also paves the way for unifying TargetIsa and MachBackend, since now they map one to one. In theory the two traits could be merged, which would be nice to limit the number of total concepts. Also they have quite different responsibilities, so it might be fine to keep them separate. Interestingly, this PR started as removing RegInfo from the TargetIsa trait since the adapter returned a dummy value there. From the fallout, noticed that all Display implementations didn't needed an ISA anymore (since these were only used to render ISA specific registers). Also the whole family of RegInfo / ValueLoc / RegUnit was exclusively used for the old backend, and these could be removed. Notably, some IR instructions needed to be removed, because they were using RegUnit too: this was the oddball of regfill / regmove / regspill / copy_special, which were IR instructions inserted by the old regalloc. Fare thee well!
67 lines
2.5 KiB
Rust
67 lines
2.5 KiB
Rust
//! Register constraints for instruction operands.
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//!
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//! An encoding recipe specifies how an instruction is encoded as binary machine code, but it only
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//! works if the operands and results satisfy certain constraints. Constraints on immediate
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//! operands are checked by instruction predicates when the recipe is chosen.
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//!
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//! It is the register allocator's job to make sure that the register constraints on value operands
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//! are satisfied.
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use crate::binemit::CodeOffset;
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/// Constraints on the range of a branch instruction.
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///
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/// A branch instruction usually encodes its destination as a signed n-bit offset from an origin.
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/// The origin depends on the ISA and the specific instruction:
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///
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/// - RISC-V and ARM Aarch64 use the address of the branch instruction, `origin = 0`.
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/// - x86 uses the address of the instruction following the branch, `origin = 2` for a 2-byte
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/// branch instruction.
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/// - ARM's A32 encoding uses the address of the branch instruction + 8 bytes, `origin = 8`.
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#[derive(Clone, Copy, Debug)]
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pub struct BranchRange {
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/// Offset in bytes from the address of the branch instruction to the origin used for computing
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/// the branch displacement. This is the destination of a branch that encodes a 0 displacement.
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pub origin: u8,
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/// Number of bits in the signed byte displacement encoded in the instruction. This does not
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/// account for branches that can only target aligned addresses.
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pub bits: u8,
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}
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impl BranchRange {
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/// Determine if this branch range can represent the range from `branch` to `dest`, where
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/// `branch` is the code offset of the branch instruction itself and `dest` is the code offset
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/// of the destination block header.
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///
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/// This method does not detect if the range is larger than 2 GB.
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pub fn contains(self, branch: CodeOffset, dest: CodeOffset) -> bool {
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let d = dest.wrapping_sub(branch + CodeOffset::from(self.origin)) as i32;
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let s = 32 - self.bits;
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d == d << s >> s
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}
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[test]
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fn branch_range() {
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// ARM T1 branch.
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let t1 = BranchRange { origin: 4, bits: 9 };
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assert!(t1.contains(0, 0));
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assert!(t1.contains(0, 2));
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assert!(t1.contains(2, 0));
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assert!(t1.contains(1000, 1000));
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// Forward limit.
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assert!(t1.contains(1000, 1258));
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assert!(!t1.contains(1000, 1260));
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// Backward limit
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assert!(t1.contains(1000, 748));
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assert!(!t1.contains(1000, 746));
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}
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}
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