This PR switches Cranelift over to the new register allocator, regalloc2. See [this document](https://gist.github.com/cfallin/08553421a91f150254fe878f67301801) for a summary of the design changes. This switchover has implications for core VCode/MachInst types and the lowering pass. Overall, this change brings improvements to both compile time and speed of generated code (runtime), as reported in #3942: ``` Benchmark Compilation (wallclock) Execution (wallclock) blake3-scalar 25% faster 28% faster blake3-simd no diff no diff meshoptimizer 19% faster 17% faster pulldown-cmark 17% faster no diff bz2 15% faster no diff SpiderMonkey, 21% faster 2% faster fib(30) clang.wasm 42% faster N/A ```
52 lines
1.6 KiB
Rust
52 lines
1.6 KiB
Rust
//! Compilation backend pipeline: optimized IR to VCode / binemit.
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use crate::ir::Function;
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use crate::isa::TargetIsa;
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use crate::machinst::*;
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use crate::timing;
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use regalloc2::RegallocOptions;
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use regalloc2::{self, MachineEnv};
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/// Compile the given function down to VCode with allocated registers, ready
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/// for binary emission.
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pub fn compile<B: LowerBackend + TargetIsa>(
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f: &Function,
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b: &B,
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abi: Box<dyn ABICallee<I = B::MInst>>,
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machine_env: &MachineEnv,
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emit_info: <B::MInst as MachInstEmit>::Info,
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) -> CodegenResult<(VCode<B::MInst>, regalloc2::Output)> {
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// Compute lowered block order.
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let block_order = BlockLoweringOrder::new(f);
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// Build the lowering context.
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let lower = Lower::new(f, abi, emit_info, block_order)?;
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// Lower the IR.
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let vcode = {
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let _tt = timing::vcode_lower();
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lower.lower(b)?
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};
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log::trace!("vcode from lowering: \n{:?}", vcode);
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// Perform register allocation.
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let regalloc_result = {
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let _tt = timing::regalloc();
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let mut options = RegallocOptions::default();
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options.verbose_log = log::log_enabled!(log::Level::Trace);
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regalloc2::run(&vcode, machine_env, &options)
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.map_err(|err| {
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log::error!(
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"Register allocation error for vcode\n{:?}\nError: {:?}\nCLIF for error:\n{:?}",
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vcode,
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err,
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f,
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);
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err
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})
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.expect("register allocation")
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};
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Ok((vcode, regalloc_result))
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}
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