9d6821d6d9
* Rename size to base_size and introduce a compute_size function; * Add infra to inspect in/outs registers when computing the size of an instruction; * Remove the GPR_SAFE_DEREF and GPR_ZERO_DEREF_SAFE register classes on x86 (fixes #335);
226 lines
6.4 KiB
Python
226 lines
6.4 KiB
Python
"""
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RISC-V Encoding recipes.
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The encoding recipes defined here more or less correspond to the RISC-V native
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instruction formats described in the reference:
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The RISC-V Instruction Set Manual
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Volume I: User-Level ISA
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Version 2.1
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"""
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from __future__ import absolute_import
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from cdsl.isa import EncRecipe
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from cdsl.predicates import IsSignedInt
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from cdsl.registers import Stack
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from base.formats import Binary, BinaryImm, MultiAry, IntCompare, IntCompareImm
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from base.formats import Unary, UnaryImm, BranchIcmp, Branch, Jump
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from base.formats import Call, CallIndirect, RegMove
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from .registers import GPR
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# The low 7 bits of a RISC-V instruction is the base opcode. All 32-bit
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# instructions have 11 as the two low bits, with bits 6:2 determining the base
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# opcode.
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#
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# Encbits for the 32-bit recipes are opcode[6:2] | (funct3 << 5) | ...
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# The functions below encode the encbits.
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def LOAD(funct3):
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# type: (int) -> int
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assert funct3 <= 0b111
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return 0b00000 | (funct3 << 5)
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def STORE(funct3):
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# type: (int) -> int
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assert funct3 <= 0b111
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return 0b01000 | (funct3 << 5)
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def BRANCH(funct3):
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# type: (int) -> int
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assert funct3 <= 0b111
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return 0b11000 | (funct3 << 5)
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def JALR(funct3=0):
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# type: (int) -> int
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assert funct3 <= 0b111
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return 0b11001 | (funct3 << 5)
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def JAL():
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# type: () -> int
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return 0b11011
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def OPIMM(funct3, funct7=0):
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# type: (int, int) -> int
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assert funct3 <= 0b111
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return 0b00100 | (funct3 << 5) | (funct7 << 8)
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def OPIMM32(funct3, funct7=0):
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# type: (int, int) -> int
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assert funct3 <= 0b111
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return 0b00110 | (funct3 << 5) | (funct7 << 8)
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def OP(funct3, funct7):
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# type: (int, int) -> int
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assert funct3 <= 0b111
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assert funct7 <= 0b1111111
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return 0b01100 | (funct3 << 5) | (funct7 << 8)
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def OP32(funct3, funct7):
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# type: (int, int) -> int
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assert funct3 <= 0b111
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assert funct7 <= 0b1111111
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return 0b01110 | (funct3 << 5) | (funct7 << 8)
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def AIUPC():
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# type: () -> int
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return 0b00101
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def LUI():
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# type: () -> int
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return 0b01101
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# R-type 32-bit instructions: These are mostly binary arithmetic instructions.
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# The encbits are `opcode[6:2] | (funct3 << 5) | (funct7 << 8)
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R = EncRecipe(
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'R', Binary, base_size=4, ins=(GPR, GPR), outs=GPR,
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emit='put_r(bits, in_reg0, in_reg1, out_reg0, sink);')
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# R-type with an immediate shift amount instead of rs2.
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Rshamt = EncRecipe(
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'Rshamt', BinaryImm, base_size=4, ins=GPR, outs=GPR,
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emit='put_rshamt(bits, in_reg0, imm.into(), out_reg0, sink);')
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# R-type encoding of an integer comparison.
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Ricmp = EncRecipe(
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'Ricmp', IntCompare, base_size=4, ins=(GPR, GPR), outs=GPR,
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emit='put_r(bits, in_reg0, in_reg1, out_reg0, sink);')
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Ii = EncRecipe(
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'Ii', BinaryImm, base_size=4, ins=GPR, outs=GPR,
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instp=IsSignedInt(BinaryImm.imm, 12),
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emit='put_i(bits, in_reg0, imm.into(), out_reg0, sink);')
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# I-type instruction with a hardcoded %x0 rs1.
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Iz = EncRecipe(
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'Iz', UnaryImm, base_size=4, ins=(), outs=GPR,
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instp=IsSignedInt(UnaryImm.imm, 12),
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emit='put_i(bits, 0, imm.into(), out_reg0, sink);')
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# I-type encoding of an integer comparison.
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Iicmp = EncRecipe(
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'Iicmp', IntCompareImm, base_size=4, ins=GPR, outs=GPR,
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instp=IsSignedInt(IntCompareImm.imm, 12),
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emit='put_i(bits, in_reg0, imm.into(), out_reg0, sink);')
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# I-type encoding for `jalr` as a return instruction. We won't use the
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# immediate offset.
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# The variable return values are not encoded.
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Iret = EncRecipe(
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'Iret', MultiAry, base_size=4, ins=(), outs=(),
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emit='''
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// Return instructions are always a jalr to %x1.
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// The return address is provided as a special-purpose link argument.
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put_i(
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bits,
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1, // rs1 = %x1
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0, // no offset.
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0, // rd = %x0: no address written.
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sink,
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);
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''')
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# I-type encoding for `jalr` as a call_indirect.
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Icall = EncRecipe(
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'Icall', CallIndirect, base_size=4, ins=GPR, outs=(),
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emit='''
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// call_indirect instructions are jalr with rd=%x1.
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put_i(
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bits,
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in_reg0,
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0, // no offset.
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1, // rd = %x1: link register.
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sink,
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);
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''')
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# Copy of a GPR is implemented as addi x, 0.
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Icopy = EncRecipe(
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'Icopy', Unary, base_size=4, ins=GPR, outs=GPR,
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emit='put_i(bits, in_reg0, 0, out_reg0, sink);')
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# Same for a GPR regmove.
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Irmov = EncRecipe(
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'Irmov', RegMove, base_size=4, ins=GPR, outs=(),
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emit='put_i(bits, src, 0, dst, sink);')
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# U-type instructions have a 20-bit immediate that targets bits 12-31.
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U = EncRecipe(
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'U', UnaryImm, base_size=4, ins=(), outs=GPR,
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instp=IsSignedInt(UnaryImm.imm, 32, 12),
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emit='put_u(bits, imm.into(), out_reg0, sink);')
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# UJ-type unconditional branch instructions.
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UJ = EncRecipe(
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'UJ', Jump, base_size=4, ins=(), outs=(), branch_range=(0, 21),
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emit='''
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let dest = i64::from(func.offsets[destination]);
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let disp = dest - i64::from(sink.offset());
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put_uj(bits, disp, 0, sink);
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''')
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UJcall = EncRecipe(
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'UJcall', Call, base_size=4, ins=(), outs=(),
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emit='''
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sink.reloc_external(Reloc::RiscvCall,
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&func.dfg.ext_funcs[func_ref].name,
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0);
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// rd=%x1 is the standard link register.
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put_uj(bits, 0, 1, sink);
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''')
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# SB-type branch instructions.
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SB = EncRecipe(
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'SB', BranchIcmp, base_size=4,
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ins=(GPR, GPR), outs=(),
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branch_range=(0, 13),
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emit='''
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let dest = i64::from(func.offsets[destination]);
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let disp = dest - i64::from(sink.offset());
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put_sb(bits, disp, in_reg0, in_reg1, sink);
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''')
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# SB-type branch instruction with rs2 fixed to zero.
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SBzero = EncRecipe(
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'SBzero', Branch, base_size=4,
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ins=(GPR), outs=(),
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branch_range=(0, 13),
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emit='''
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let dest = i64::from(func.offsets[destination]);
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let disp = dest - i64::from(sink.offset());
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put_sb(bits, disp, in_reg0, 0, sink);
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''')
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# Spill of a GPR.
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GPsp = EncRecipe(
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'GPsp', Unary, base_size=4,
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ins=GPR, outs=Stack(GPR),
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emit='unimplemented!();')
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# Fill of a GPR.
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GPfi = EncRecipe(
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'GPfi', Unary, base_size=4,
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ins=Stack(GPR), outs=GPR,
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emit='unimplemented!();')
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