0508932174
* cranelift: Reorganize test suite Group some SIMD operations by instruction. * cranelift: Deduplicate some shift tests Also, new tests with the mod behaviour * aarch64: Lower shifts with mod behaviour * x64: Lower shifts with mod behaviour * wasmtime: Don't mask SIMD shifts
59 lines
1.7 KiB
Plaintext
59 lines
1.7 KiB
Plaintext
test run
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set enable_simd
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target aarch64
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target s390x
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target x86_64 skylake
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function %sshr_i8x16(i8x16, i32) -> i8x16 {
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block0(v0: i8x16, v1: i32):
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v2 = sshr v0, v1
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return v2
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}
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; run: %sshr_i8x16([0 0xff 2 0xfd 4 0xfb 6 0xf9 8 0xf7 10 0xf5 12 0xf3 14 0xf1], 1) == [0 0xff 1 0xfe 2 0xfd 3 0xfc 4 0xfb 5 0xfa 6 0xf9 7 0xf8]
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; run: %sshr_i8x16([0 0xff 2 0xfd 4 0xfb 6 0xf9 8 0xf7 10 0xf5 12 0xf3 14 0xf1], 9) == [0 0xff 1 0xfe 2 0xfd 3 0xfc 4 0xfb 5 0xfa 6 0xf9 7 0xf8]
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function %sshr_i16x8(i16x8, i32) -> i16x8 {
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block0(v0: i16x8, v1: i32):
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v2 = sshr v0, v1
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return v2
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}
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; note: because of the shifted-in sign-bit, lane 0 remains -1 == 0xffff, whereas lane 4 has been shifted to -8 == 0xfff8
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; run: %sshr_i16x8([-1 2 4 8 -16 32 64 128], 1) == [-1 1 2 4 -8 16 32 64]
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; run: %sshr_i16x8([-1 2 4 8 -16 32 64 128], 17) == [-1 1 2 4 -8 16 32 64]
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function %sshr_i32x4(i32x4, i32) -> i32x4 {
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block0(v0: i32x4, v1: i32):
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v2 = sshr v0, v1
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return v2
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}
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; run: %sshr_i32x4([1 2 4 -8], 1) == [0 1 2 -4]
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; run: %sshr_i32x4([1 2 4 -8], 33) == [0 1 2 -4]
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function %sshr_i64x2(i64x2, i32) -> i64x2 {
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block0(v0:i64x2, v1:i32):
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v2 = sshr v0, v1
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return v2
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}
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; run: %sshr_i64x2([1 -1], 0) == [1 -1]
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; run: %sshr_i64x2([1 -1], 1) == [0 -1] ; note the -1 shift result
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; run: %sshr_i64x2([2 -2], 1) == [1 -1]
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; run: %sshr_i64x2([0x80000000_00000000 0x7FFFFFFF_FFFFFFFF], 63) == [0xFFFFFFFF_FFFFFFFF 0]
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; run: %sshr_i64x2([2 -2], 65) == [1 -1]
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function %sshr_imm_i32x4(i32x4) -> i32x4 {
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block0(v0: i32x4):
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v1 = sshr_imm v0, 1
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return v1
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}
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; run: %sshr_imm_i32x4([1 2 4 -8]) == [0 1 2 -4]
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function %sshr_imm_i16x8(i16x8) -> i16x8 {
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block0(v0: i16x8):
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v1 = sshr_imm v0, 1
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return v1
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}
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; run: %sshr_imm_i16x8([1 2 4 -8 0 0 0 0]) == [0 1 2 -4 0 0 0 0]
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