dd40bf075a
This enables more runtests to be executed on s390x. Doing so
uncovered a two back-end bugs, which are fixed as well:
- The result of cls was always off by one.
- The result of popcnt.i16 has uninitialized high bits.
In addition, I found a bug in the load-op-store.clif test case:
v3 = heap_addr.i64 heap0, v1, 4
v4 = iconst.i64 42
store.i32 v4, v3
This was clearly intended to perform a 32-bit store, but
actually performs a 64-bit store (it seems the type annotation
of the store opcode is ignored, and the type of the operand
is used instead). That bug did not show any noticable symptoms
on little-endian architectures, but broke on big-endian.
43 lines
739 B
Plaintext
43 lines
739 B
Plaintext
test interpret
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test run
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target aarch64
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target s390x
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target x86_64
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target x86_64 has_bmi1
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function %ctz_i8(i8) -> i8 {
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block0(v0: i8):
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v1 = ctz v0
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return v1
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}
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; run: %ctz_i8(1) == 0
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; run: %ctz_i8(0x40) == 6
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; run: %ctz_i8(-1) == 0
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function %ctz_i16(i16) -> i16 {
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block0(v0: i16):
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v1 = ctz v0
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return v1
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}
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; run: %ctz_i16(1) == 0
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; run: %ctz_i16(0x4000) == 14
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; run: %ctz_i16(-1) == 0
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function %ctz_i32(i32) -> i32 {
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block0(v0: i32):
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v1 = ctz v0
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return v1
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}
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; run: %ctz_i32(1) == 0
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; run: %ctz_i32(0x40000000) == 30
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; run: %ctz_i32(-1) == 0
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function %ctz_i64(i64) -> i64 {
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block0(v0: i64):
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v1 = ctz v0
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return v1
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}
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; run: %ctz_i64(1) == 0
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; run: %ctz_i64(0x4000000000000000) == 62
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; run: %ctz_i64(-1) == 0
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