8b484b1c77
* Function names should start with % * Create FunctionName from string * Implement displaying of FunctionName as %nnnn with fallback to #xxxx * Run rustfmt and fix FunctionName::with_string in parser * Implement FunctionName::new as a generic function * Binary function names should start with # * Implement NameRepr for function name * Fix examples in docs to reflect that function names start with % * Rebase and fix filecheck tests
202 lines
8.3 KiB
Plaintext
202 lines
8.3 KiB
Plaintext
; binary emission of 32-bit code.
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test binemit
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isa intel
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; The binary encodings can be verified with the command:
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;
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; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary32.cton | llvm-mc -show-encoding -triple=i386
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;
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function %I32() {
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ebb0:
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[-,%rcx] v1 = iconst.i32 1
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[-,%rsi] v2 = iconst.i32 2
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; Integer Register-Register Operations.
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; asm: addl %esi, %ecx
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[-,%rcx] v10 = iadd v1, v2 ; bin: 01 f1
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; asm: addl %ecx, %esi
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[-,%rsi] v11 = iadd v2, v1 ; bin: 01 ce
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; asm: subl %esi, %ecx
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[-,%rcx] v12 = isub v1, v2 ; bin: 29 f1
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; asm: subl %ecx, %esi
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[-,%rsi] v13 = isub v2, v1 ; bin: 29 ce
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; asm: andl %esi, %ecx
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[-,%rcx] v14 = band v1, v2 ; bin: 21 f1
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; asm: andl %ecx, %esi
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[-,%rsi] v15 = band v2, v1 ; bin: 21 ce
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; asm: orl %esi, %ecx
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[-,%rcx] v16 = bor v1, v2 ; bin: 09 f1
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; asm: orl %ecx, %esi
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[-,%rsi] v17 = bor v2, v1 ; bin: 09 ce
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; asm: xorl %esi, %ecx
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[-,%rcx] v18 = bxor v1, v2 ; bin: 31 f1
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; asm: xorl %ecx, %esi
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[-,%rsi] v19 = bxor v2, v1 ; bin: 31 ce
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; Dynamic shifts take the shift amount in %rcx.
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; asm: shll %cl, %esi
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[-,%rsi] v20 = ishl v2, v1 ; bin: d3 e6
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; asm: shll %cl, %ecx
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[-,%rcx] v21 = ishl v1, v1 ; bin: d3 e1
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; asm: shrl %cl, %esi
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[-,%rsi] v22 = ushr v2, v1 ; bin: d3 ee
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; asm: shrl %cl, %ecx
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[-,%rcx] v23 = ushr v1, v1 ; bin: d3 e9
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; asm: sarl %cl, %esi
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[-,%rsi] v24 = sshr v2, v1 ; bin: d3 fe
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; asm: sarl %cl, %ecx
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[-,%rcx] v25 = sshr v1, v1 ; bin: d3 f9
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; Integer Register - Immediate 8-bit operations.
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; The 8-bit immediate is sign-extended.
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; asm: addl $-128, %ecx
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[-,%rcx] v30 = iadd_imm v1, -128 ; bin: 83 c1 80
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; asm: addl $10, %esi
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[-,%rsi] v31 = iadd_imm v2, 10 ; bin: 83 c6 0a
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; asm: andl $-128, %ecx
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[-,%rcx] v32 = band_imm v1, -128 ; bin: 83 e1 80
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; asm: andl $10, %esi
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[-,%rsi] v33 = band_imm v2, 10 ; bin: 83 e6 0a
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; asm: orl $-128, %ecx
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[-,%rcx] v34 = bor_imm v1, -128 ; bin: 83 c9 80
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; asm: orl $10, %esi
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[-,%rsi] v35 = bor_imm v2, 10 ; bin: 83 ce 0a
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; asm: xorl $-128, %ecx
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[-,%rcx] v36 = bxor_imm v1, -128 ; bin: 83 f1 80
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; asm: xorl $10, %esi
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[-,%rsi] v37 = bxor_imm v2, 10 ; bin: 83 f6 0a
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; Integer Register - Immediate 32-bit operations.
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; asm: addl $-128000, %ecx
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[-,%rcx] v40 = iadd_imm v1, -128000 ; bin: 81 c1 fffe0c00
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; asm: addl $1000000, %esi
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[-,%rsi] v41 = iadd_imm v2, 1000000 ; bin: 81 c6 000f4240
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; asm: andl $-128000, %ecx
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[-,%rcx] v42 = band_imm v1, -128000 ; bin: 81 e1 fffe0c00
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; asm: andl $1000000, %esi
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[-,%rsi] v43 = band_imm v2, 1000000 ; bin: 81 e6 000f4240
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; asm: orl $-128000, %ecx
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[-,%rcx] v44 = bor_imm v1, -128000 ; bin: 81 c9 fffe0c00
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; asm: orl $1000000, %esi
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[-,%rsi] v45 = bor_imm v2, 1000000 ; bin: 81 ce 000f4240
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; asm: xorl $-128000, %ecx
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[-,%rcx] v46 = bxor_imm v1, -128000 ; bin: 81 f1 fffe0c00
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; asm: xorl $1000000, %esi
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[-,%rsi] v47 = bxor_imm v2, 1000000 ; bin: 81 f6 000f4240
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; Load/Store instructions.
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; Register indirect addressing with no displacement.
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; asm: movl %ecx, (%esi)
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store v1, v2 ; bin: 89 0e
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; asm: movl %esi, (%ecx)
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store v2, v1 ; bin: 89 31
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; asm: movw %cx, (%esi)
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istore16 v1, v2 ; bin: 66 89 0e
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; asm: movw %si, (%ecx)
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istore16 v2, v1 ; bin: 66 89 31
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; asm: movb %cl, (%esi)
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istore8 v1, v2 ; bin: 88 0e
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; Can't store %sil in 32-bit mode (needs REX prefix).
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; asm: movl (%ecx), %edi
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[-,%rdi] v100 = load.i32 v1 ; bin: 8b 39
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; asm: movl (%esi), %edx
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[-,%rdx] v101 = load.i32 v2 ; bin: 8b 16
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; asm: movzwl (%ecx), %edi
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[-,%rdi] v102 = uload16.i32 v1 ; bin: 0f b7 39
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; asm: movzwl (%esi), %edx
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[-,%rdx] v103 = uload16.i32 v2 ; bin: 0f b7 16
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; asm: movswl (%ecx), %edi
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[-,%rdi] v104 = sload16.i32 v1 ; bin: 0f bf 39
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; asm: movswl (%esi), %edx
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[-,%rdx] v105 = sload16.i32 v2 ; bin: 0f bf 16
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; asm: movzbl (%ecx), %edi
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[-,%rdi] v106 = uload8.i32 v1 ; bin: 0f b6 39
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; asm: movzbl (%esi), %edx
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[-,%rdx] v107 = uload8.i32 v2 ; bin: 0f b6 16
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; asm: movsbl (%ecx), %edi
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[-,%rdi] v108 = sload8.i32 v1 ; bin: 0f be 39
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; asm: movsbl (%esi), %edx
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[-,%rdx] v109 = sload8.i32 v2 ; bin: 0f be 16
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; Register-indirect with 8-bit signed displacement.
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; asm: movl %ecx, 100(%esi)
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store v1, v2+100 ; bin: 89 4e 64
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; asm: movl %esi, -100(%ecx)
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store v2, v1-100 ; bin: 89 71 9c
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; asm: movw %cx, 100(%esi)
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istore16 v1, v2+100 ; bin: 66 89 4e 64
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; asm: movw %si, -100(%ecx)
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istore16 v2, v1-100 ; bin: 66 89 71 9c
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; asm: movb %cl, 100(%esi)
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istore8 v1, v2+100 ; bin: 88 4e 64
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; asm: movl 50(%ecx), %edi
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[-,%rdi] v110 = load.i32 v1+50 ; bin: 8b 79 32
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; asm: movl -50(%esi), %edx
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[-,%rdx] v111 = load.i32 v2-50 ; bin: 8b 56 ce
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; asm: movzwl 50(%ecx), %edi
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[-,%rdi] v112 = uload16.i32 v1+50 ; bin: 0f b7 79 32
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; asm: movzwl -50(%esi), %edx
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[-,%rdx] v113 = uload16.i32 v2-50 ; bin: 0f b7 56 ce
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; asm: movswl 50(%ecx), %edi
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[-,%rdi] v114 = sload16.i32 v1+50 ; bin: 0f bf 79 32
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; asm: movswl -50(%esi), %edx
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[-,%rdx] v115 = sload16.i32 v2-50 ; bin: 0f bf 56 ce
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; asm: movzbl 50(%ecx), %edi
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[-,%rdi] v116 = uload8.i32 v1+50 ; bin: 0f b6 79 32
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; asm: movzbl -50(%esi), %edx
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[-,%rdx] v117 = uload8.i32 v2-50 ; bin: 0f b6 56 ce
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; asm: movsbl 50(%ecx), %edi
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[-,%rdi] v118 = sload8.i32 v1+50 ; bin: 0f be 79 32
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; asm: movsbl -50(%esi), %edx
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[-,%rdx] v119 = sload8.i32 v2-50 ; bin: 0f be 56 ce
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; Register-indirect with 32-bit signed displacement.
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; asm: movl %ecx, 10000(%esi)
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store v1, v2+10000 ; bin: 89 8e 00002710
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; asm: movl %esi, -10000(%ecx)
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store v2, v1-10000 ; bin: 89 b1 ffffd8f0
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; asm: movw %cx, 10000(%esi)
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istore16 v1, v2+10000 ; bin: 66 89 8e 00002710
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; asm: movw %si, -10000(%ecx)
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istore16 v2, v1-10000 ; bin: 66 89 b1 ffffd8f0
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; asm: movb %cl, 10000(%esi)
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istore8 v1, v2+10000 ; bin: 88 8e 00002710
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; asm: movl 50000(%ecx), %edi
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[-,%rdi] v120 = load.i32 v1+50000 ; bin: 8b b9 0000c350
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; asm: movl -50000(%esi), %edx
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[-,%rdx] v121 = load.i32 v2-50000 ; bin: 8b 96 ffff3cb0
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; asm: movzwl 50000(%ecx), %edi
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[-,%rdi] v122 = uload16.i32 v1+50000 ; bin: 0f b7 b9 0000c350
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; asm: movzwl -50000(%esi), %edx
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[-,%rdx] v123 = uload16.i32 v2-50000 ; bin: 0f b7 96 ffff3cb0
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; asm: movswl 50000(%ecx), %edi
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[-,%rdi] v124 = sload16.i32 v1+50000 ; bin: 0f bf b9 0000c350
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; asm: movswl -50000(%esi), %edx
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[-,%rdx] v125 = sload16.i32 v2-50000 ; bin: 0f bf 96 ffff3cb0
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; asm: movzbl 50000(%ecx), %edi
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[-,%rdi] v126 = uload8.i32 v1+50000 ; bin: 0f b6 b9 0000c350
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; asm: movzbl -50000(%esi), %edx
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[-,%rdx] v127 = uload8.i32 v2-50000 ; bin: 0f b6 96 ffff3cb0
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; asm: movsbl 50000(%ecx), %edi
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[-,%rdi] v128 = sload8.i32 v1+50000 ; bin: 0f be b9 0000c350
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; asm: movsbl -50000(%esi), %edx
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[-,%rdx] v129 = sload8.i32 v2-50000 ; bin: 0f be 96 ffff3cb0
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return
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}
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