cdecc858b4
Add a RISC-V 64 (`riscv64`, RV64GC) backend. Co-authored-by: yuyang <756445638@qq.com> Co-authored-by: Chris Fallin <chris@cfallin.org> Co-authored-by: Afonso Bordado <afonsobordado@az8.co>
32 lines
742 B
Plaintext
32 lines
742 B
Plaintext
test interpret
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test run
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target aarch64
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set enable_simd
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target x86_64 has_sse3 has_ssse3 has_sse41
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target s390x
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target riscv64
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function %umulhi_i16(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = umulhi v0, v1
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return v2
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}
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; run: %umulhi_i16(2, 4) == 0
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; run: %umulhi_i16(65535, 65535) == 65534
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function %umulhi_i32(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = umulhi v0, v1
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return v2
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}
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; run: %umulhi_i32(500, 700) == 0
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; run: %umulhi_i32(4294967295, 4294967295) == 4294967294
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function %umulhi_i64(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = umulhi v0, v1
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return v2
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}
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; run: %umulhi_i64(4294967295, 4294967295) == 0
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; run: %umulhi_i64(18446744073709551615, 18446744073709551615) == 18446744073709551614
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