9629867d0c
We don't support the full set of Intel addressing modes yet. So far we have: - Register indirect, no displacement. - Register indirect, 8-bit signed displacement. - Register indirect, 32-bit signed displacement. The SIB addressing modes will need new Cretonne instruction formats to represent.
65 lines
2.4 KiB
Python
65 lines
2.4 KiB
Python
"""
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Intel Encodings.
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"""
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from __future__ import absolute_import
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from base import instructions as base
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from .defs import I32
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from . import recipes as rcp
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from .recipes import OP, OP0F, MP66
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I32.enc(base.iadd.i32, rcp.Op1rr, OP(0x01))
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I32.enc(base.isub.i32, rcp.Op1rr, OP(0x29))
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I32.enc(base.band.i32, rcp.Op1rr, OP(0x21))
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I32.enc(base.bor.i32, rcp.Op1rr, OP(0x09))
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I32.enc(base.bxor.i32, rcp.Op1rr, OP(0x31))
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# Immediate instructions with sign-extended 8-bit and 32-bit immediate.
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for inst, r in [
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(base.iadd_imm.i32, 0),
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(base.band_imm.i32, 4),
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(base.bor_imm.i32, 1),
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(base.bxor_imm.i32, 6)]:
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I32.enc(inst, rcp.Op1rib, OP(0x83, rrr=r))
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I32.enc(inst, rcp.Op1rid, OP(0x81, rrr=r))
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# 32-bit shifts and rotates.
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# Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit
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# and 16-bit shifts would need explicit masking.
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I32.enc(base.ishl.i32.i32, rcp.Op1rc, OP(0xd3, rrr=4))
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I32.enc(base.ushr.i32.i32, rcp.Op1rc, OP(0xd3, rrr=5))
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I32.enc(base.sshr.i32.i32, rcp.Op1rc, OP(0xd3, rrr=7))
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# Loads and stores.
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I32.enc(base.store.i32.i32, rcp.Op1st, OP(0x89))
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I32.enc(base.store.i32.i32, rcp.Op1stDisp8, OP(0x89))
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I32.enc(base.store.i32.i32, rcp.Op1stDisp32, OP(0x89))
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I32.enc(base.istore16.i32.i32, rcp.Mp1st, MP66(0x89))
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I32.enc(base.istore16.i32.i32, rcp.Mp1stDisp8, MP66(0x89))
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I32.enc(base.istore16.i32.i32, rcp.Mp1stDisp32, MP66(0x89))
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I32.enc(base.istore8.i32.i32, rcp.Op1st_abcd, OP(0x88))
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I32.enc(base.istore8.i32.i32, rcp.Op1stDisp8_abcd, OP(0x88))
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I32.enc(base.istore8.i32.i32, rcp.Op1stDisp32_abcd, OP(0x88))
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I32.enc(base.load.i32.i32, rcp.Op1ld, OP(0x8b))
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I32.enc(base.load.i32.i32, rcp.Op1ldDisp8, OP(0x8b))
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I32.enc(base.load.i32.i32, rcp.Op1ldDisp32, OP(0x8b))
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I32.enc(base.uload16.i32.i32, rcp.Op2ld, OP0F(0xb7))
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I32.enc(base.uload16.i32.i32, rcp.Op2ldDisp8, OP0F(0xb7))
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I32.enc(base.uload16.i32.i32, rcp.Op2ldDisp32, OP0F(0xb7))
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I32.enc(base.sload16.i32.i32, rcp.Op2ld, OP0F(0xbf))
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I32.enc(base.sload16.i32.i32, rcp.Op2ldDisp8, OP0F(0xbf))
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I32.enc(base.sload16.i32.i32, rcp.Op2ldDisp32, OP0F(0xbf))
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I32.enc(base.uload8.i32.i32, rcp.Op2ld, OP0F(0xb6))
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I32.enc(base.uload8.i32.i32, rcp.Op2ldDisp8, OP0F(0xb6))
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I32.enc(base.uload8.i32.i32, rcp.Op2ldDisp32, OP0F(0xb6))
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I32.enc(base.sload8.i32.i32, rcp.Op2ld, OP0F(0xbe))
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I32.enc(base.sload8.i32.i32, rcp.Op2ldDisp8, OP0F(0xbe))
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I32.enc(base.sload8.i32.i32, rcp.Op2ldDisp32, OP0F(0xbe))
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