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wasmtime/cranelift/codegen
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Afonso Bordado 62cbb5045e riscv64: Implement a few SIMD arithmetic ops (#6268) 
* riscv64: Swap order of `VecAluRRR` source registers

These were accidentally reversed from what we declare in the isle emit helper

* riscv64: Add SIMD `isub`

* riscv64: Add SIMD `imul`

* riscv64: Add `{u,s}mulhi`

* riscv64: Add `b{and,or,xor}`

* cranelift: Move `imul.i8x16` runtest to separate file

Looks like x86 does not implement it

* riscv64: Better formatting for `VecAluOpRRR`

* cranelift: Enable x86 SIMD tests with `has_sse41=false`
2023-04-25 16:39:33 +00:00
..
benches
deps: update criterion dependency to v0.4.0 (#5935)
2023-03-07 15:21:48 +00:00
meta
riscv64: Support non 128bit vector sizes (#6266)
2023-04-25 14:50:00 +00:00
shared
Bump Wasmtime to 9.0.0 (#6143)
2023-04-05 17:06:36 +00:00
src
riscv64: Implement a few SIMD arithmetic ops (#6268)
2023-04-25 16:39:33 +00:00
build.rs
riscv64: Initial SIMD Vector Implementation (#6240)
2023-04-20 21:54:43 +00:00
Cargo.toml
Bump regalloc2 to 0.7.0 (#6237)
2023-04-21 00:47:58 +00:00
LICENSE
moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
2019-01-28 15:56:54 -08:00
README.md
moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
2019-01-28 15:56:54 -08:00

README.md

This crate contains the core Cranelift code generator. It translates code from an intermediate representation into executable machine code.