955d4e4ba1
This retains `lower_amode` in the handwritten code (@akirilov-arm reports that there is an upcoming patch to port this), but tweaks it slightly to take a `Value` rather than an `Inst`.
776 lines
25 KiB
Rust
776 lines
25 KiB
Rust
//! AArch64 ISA definitions: instruction arguments.
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use crate::ir::types::*;
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use crate::ir::Type;
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use crate::isa::aarch64::inst::*;
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use crate::machinst::{ty_bits, MachLabel, PrettyPrint, Reg, Writable};
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use core::convert::Into;
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use std::string::String;
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//=============================================================================
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// Instruction sub-components: shift and extend descriptors
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/// A shift operator for a register or immediate.
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#[derive(Clone, Copy, Debug)]
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#[repr(u8)]
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pub enum ShiftOp {
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LSL = 0b00,
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#[allow(dead_code)]
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LSR = 0b01,
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#[allow(dead_code)]
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ASR = 0b10,
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#[allow(dead_code)]
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ROR = 0b11,
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}
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impl ShiftOp {
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/// Get the encoding of this shift op.
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pub fn bits(self) -> u8 {
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self as u8
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}
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}
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/// A shift operator amount.
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#[derive(Clone, Copy, Debug)]
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pub struct ShiftOpShiftImm(u8);
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impl ShiftOpShiftImm {
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/// Maximum shift for shifted-register operands.
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pub const MAX_SHIFT: u64 = 63;
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/// Create a new shiftop shift amount, if possible.
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pub fn maybe_from_shift(shift: u64) -> Option<ShiftOpShiftImm> {
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if shift <= Self::MAX_SHIFT {
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Some(ShiftOpShiftImm(shift as u8))
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} else {
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None
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}
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}
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/// Return the shift amount.
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pub fn value(self) -> u8 {
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self.0
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}
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/// Mask down to a given number of bits.
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pub fn mask(self, bits: u8) -> ShiftOpShiftImm {
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ShiftOpShiftImm(self.0 & (bits - 1))
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}
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}
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/// A shift operator with an amount, guaranteed to be within range.
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#[derive(Copy, Clone, Debug)]
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pub struct ShiftOpAndAmt {
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op: ShiftOp,
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shift: ShiftOpShiftImm,
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}
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impl ShiftOpAndAmt {
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pub fn new(op: ShiftOp, shift: ShiftOpShiftImm) -> ShiftOpAndAmt {
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ShiftOpAndAmt { op, shift }
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}
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/// Get the shift op.
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pub fn op(&self) -> ShiftOp {
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self.op
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}
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/// Get the shift amount.
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pub fn amt(&self) -> ShiftOpShiftImm {
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self.shift
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}
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}
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/// An extend operator for a register.
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#[derive(Clone, Copy, Debug)]
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#[repr(u8)]
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pub enum ExtendOp {
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UXTB = 0b000,
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UXTH = 0b001,
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UXTW = 0b010,
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UXTX = 0b011,
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SXTB = 0b100,
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SXTH = 0b101,
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SXTW = 0b110,
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#[allow(dead_code)]
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SXTX = 0b111,
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}
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impl ExtendOp {
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/// Encoding of this op.
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pub fn bits(self) -> u8 {
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self as u8
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}
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}
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//=============================================================================
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// Instruction sub-components (memory addresses): definitions
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/// A reference to some memory address.
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#[derive(Clone, Debug)]
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pub enum MemLabel {
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/// An address in the code, a constant pool or jumptable, with relative
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/// offset from this instruction. This form must be used at emission time;
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/// see `memlabel_finalize()` for how other forms are lowered to this one.
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PCRel(i32),
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}
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/// An addressing mode specified for a load/store operation.
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#[derive(Clone, Debug)]
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pub enum AMode {
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//
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// Real ARM64 addressing modes:
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//
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/// "post-indexed" mode as per AArch64 docs: postincrement reg after address computation.
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PostIndexed(Writable<Reg>, SImm9),
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/// "pre-indexed" mode as per AArch64 docs: preincrement reg before address computation.
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PreIndexed(Writable<Reg>, SImm9),
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// N.B.: RegReg, RegScaled, and RegScaledExtended all correspond to
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// what the ISA calls the "register offset" addressing mode. We split out
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// several options here for more ergonomic codegen.
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/// Register plus register offset.
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RegReg(Reg, Reg),
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#[allow(dead_code)]
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/// Register plus register offset, scaled by type's size.
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RegScaled(Reg, Reg, Type),
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/// Register plus register offset, scaled by type's size, with index sign- or zero-extended
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/// first.
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RegScaledExtended(Reg, Reg, Type, ExtendOp),
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/// Register plus register offset, with index sign- or zero-extended first.
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RegExtended(Reg, Reg, ExtendOp),
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/// Unscaled signed 9-bit immediate offset from reg.
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Unscaled(Reg, SImm9),
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/// Scaled (by size of a type) unsigned 12-bit immediate offset from reg.
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UnsignedOffset(Reg, UImm12Scaled),
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//
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// virtual addressing modes that are lowered at emission time:
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//
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/// Reference to a "label": e.g., a symbol.
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Label(MemLabel),
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/// Arbitrary offset from a register. Converted to generation of large
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/// offsets with multiple instructions as necessary during code emission.
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RegOffset(Reg, i64, Type),
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/// Offset from the stack pointer.
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SPOffset(i64, Type),
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/// Offset from the frame pointer.
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FPOffset(i64, Type),
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/// Offset from the "nominal stack pointer", which is where the real SP is
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/// just after stack and spill slots are allocated in the function prologue.
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/// At emission time, this is converted to `SPOffset` with a fixup added to
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/// the offset constant. The fixup is a running value that is tracked as
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/// emission iterates through instructions in linear order, and can be
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/// adjusted up and down with [Inst::VirtualSPOffsetAdj].
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///
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/// The standard ABI is in charge of handling this (by emitting the
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/// adjustment meta-instructions). It maintains the invariant that "nominal
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/// SP" is where the actual SP is after the function prologue and before
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/// clobber pushes. See the diagram in the documentation for
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/// [crate::isa::aarch64::abi](the ABI module) for more details.
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NominalSPOffset(i64, Type),
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}
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impl AMode {
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/// Memory reference using an address in a register.
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pub fn reg(reg: Reg) -> AMode {
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// Use UnsignedOffset rather than Unscaled to use ldr rather than ldur.
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// This also does not use PostIndexed / PreIndexed as they update the register.
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AMode::UnsignedOffset(reg, UImm12Scaled::zero(I64))
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}
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/// Memory reference using `reg1 + sizeof(ty) * reg2` as an address, with `reg2` sign- or
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/// zero-extended as per `op`.
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pub fn reg_plus_reg_scaled_extended(reg1: Reg, reg2: Reg, ty: Type, op: ExtendOp) -> AMode {
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AMode::RegScaledExtended(reg1, reg2, ty, op)
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}
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/// Does the address resolve to just a register value, with no offset or
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/// other computation?
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pub fn is_reg(&self) -> Option<Reg> {
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match self {
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&AMode::UnsignedOffset(r, uimm12) if uimm12.value() == 0 => Some(r),
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&AMode::Unscaled(r, imm9) if imm9.value() == 0 => Some(r),
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&AMode::RegOffset(r, off, _) if off == 0 => Some(r),
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&AMode::FPOffset(off, _) if off == 0 => Some(fp_reg()),
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&AMode::SPOffset(off, _) if off == 0 => Some(stack_reg()),
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_ => None,
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}
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}
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pub fn with_allocs(&self, allocs: &mut AllocationConsumer<'_>) -> Self {
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// This should match `memarg_operands()`.
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match self {
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&AMode::Unscaled(reg, imm9) => AMode::Unscaled(allocs.next(reg), imm9),
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&AMode::UnsignedOffset(r, uimm12) => AMode::UnsignedOffset(allocs.next(r), uimm12),
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&AMode::RegReg(r1, r2) => AMode::RegReg(allocs.next(r1), allocs.next(r2)),
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&AMode::RegScaled(r1, r2, ty) => AMode::RegScaled(allocs.next(r1), allocs.next(r2), ty),
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&AMode::RegScaledExtended(r1, r2, ty, ext) => {
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AMode::RegScaledExtended(allocs.next(r1), allocs.next(r2), ty, ext)
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}
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&AMode::RegExtended(r1, r2, ext) => {
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AMode::RegExtended(allocs.next(r1), allocs.next(r2), ext)
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}
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&AMode::PreIndexed(reg, simm9) => AMode::PreIndexed(allocs.next_writable(reg), simm9),
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&AMode::PostIndexed(reg, simm9) => AMode::PostIndexed(allocs.next_writable(reg), simm9),
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&AMode::RegOffset(r, off, ty) => AMode::RegOffset(allocs.next(r), off, ty),
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&AMode::FPOffset(..)
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| &AMode::SPOffset(..)
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| &AMode::NominalSPOffset(..)
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| AMode::Label(..) => self.clone(),
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}
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}
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}
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/// A memory argument to a load/store-pair.
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#[derive(Clone, Debug)]
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pub enum PairAMode {
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SignedOffset(Reg, SImm7Scaled),
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PreIndexed(Writable<Reg>, SImm7Scaled),
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PostIndexed(Writable<Reg>, SImm7Scaled),
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}
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impl PairAMode {
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pub fn with_allocs(&self, allocs: &mut AllocationConsumer<'_>) -> Self {
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// Should match `pairmemarg_operands()`.
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match self {
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&PairAMode::SignedOffset(reg, simm7scaled) => {
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PairAMode::SignedOffset(allocs.next(reg), simm7scaled)
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}
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&PairAMode::PreIndexed(reg, simm7scaled) => {
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PairAMode::PreIndexed(allocs.next_writable(reg), simm7scaled)
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}
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&PairAMode::PostIndexed(reg, simm7scaled) => {
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PairAMode::PostIndexed(allocs.next_writable(reg), simm7scaled)
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}
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}
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}
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}
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//=============================================================================
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// Instruction sub-components (conditions, branches and branch targets):
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// definitions
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/// Condition for conditional branches.
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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#[repr(u8)]
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pub enum Cond {
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Eq = 0,
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Ne = 1,
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Hs = 2,
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Lo = 3,
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Mi = 4,
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Pl = 5,
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Vs = 6,
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Vc = 7,
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Hi = 8,
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Ls = 9,
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Ge = 10,
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Lt = 11,
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Gt = 12,
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Le = 13,
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Al = 14,
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Nv = 15,
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}
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impl Cond {
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/// Return the inverted condition.
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pub fn invert(self) -> Cond {
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match self {
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Cond::Eq => Cond::Ne,
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Cond::Ne => Cond::Eq,
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Cond::Hs => Cond::Lo,
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Cond::Lo => Cond::Hs,
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Cond::Mi => Cond::Pl,
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Cond::Pl => Cond::Mi,
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Cond::Vs => Cond::Vc,
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Cond::Vc => Cond::Vs,
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Cond::Hi => Cond::Ls,
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Cond::Ls => Cond::Hi,
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Cond::Ge => Cond::Lt,
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Cond::Lt => Cond::Ge,
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Cond::Gt => Cond::Le,
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Cond::Le => Cond::Gt,
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Cond::Al => Cond::Nv,
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Cond::Nv => Cond::Al,
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}
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}
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/// Return the machine encoding of this condition.
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pub fn bits(self) -> u32 {
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self as u32
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}
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}
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/// The kind of conditional branch: the common-case-optimized "reg-is-zero" /
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/// "reg-is-nonzero" variants, or the generic one that tests the machine
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/// condition codes.
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#[derive(Clone, Copy, Debug)]
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pub enum CondBrKind {
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/// Condition: given register is zero.
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Zero(Reg),
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/// Condition: given register is nonzero.
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NotZero(Reg),
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/// Condition: the given condition-code test is true.
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Cond(Cond),
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}
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impl CondBrKind {
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/// Return the inverted branch condition.
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pub fn invert(self) -> CondBrKind {
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match self {
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CondBrKind::Zero(reg) => CondBrKind::NotZero(reg),
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CondBrKind::NotZero(reg) => CondBrKind::Zero(reg),
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CondBrKind::Cond(c) => CondBrKind::Cond(c.invert()),
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}
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}
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}
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/// A branch target. Either unresolved (basic-block index) or resolved (offset
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/// from end of current instruction).
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub enum BranchTarget {
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/// An unresolved reference to a Label, as passed into
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/// `lower_branch_group()`.
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Label(MachLabel),
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/// A fixed PC offset.
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ResolvedOffset(i32),
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}
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impl BranchTarget {
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/// Return the target's label, if it is a label-based target.
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pub fn as_label(self) -> Option<MachLabel> {
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match self {
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BranchTarget::Label(l) => Some(l),
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_ => None,
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}
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}
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/// Return the target's offset, if specified, or zero if label-based.
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pub fn as_offset19_or_zero(self) -> u32 {
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let off = match self {
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BranchTarget::ResolvedOffset(off) => off >> 2,
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_ => 0,
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};
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assert!(off <= 0x3ffff);
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assert!(off >= -0x40000);
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(off as u32) & 0x7ffff
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}
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/// Return the target's offset, if specified, or zero if label-based.
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pub fn as_offset26_or_zero(self) -> u32 {
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let off = match self {
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BranchTarget::ResolvedOffset(off) => off >> 2,
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_ => 0,
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};
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assert!(off <= 0x1ffffff);
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assert!(off >= -0x2000000);
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(off as u32) & 0x3ffffff
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}
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}
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impl PrettyPrint for ShiftOpAndAmt {
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fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
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format!("{:?} {}", self.op(), self.amt().value())
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}
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}
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impl PrettyPrint for ExtendOp {
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fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
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format!("{:?}", self)
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}
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}
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impl PrettyPrint for MemLabel {
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fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
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match self {
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&MemLabel::PCRel(off) => format!("pc+{}", off),
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}
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}
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}
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fn shift_for_type(ty: Type) -> usize {
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match ty.bytes() {
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1 => 0,
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2 => 1,
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4 => 2,
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8 => 3,
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16 => 4,
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_ => panic!("unknown type: {}", ty),
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}
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}
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impl PrettyPrint for AMode {
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fn pretty_print(&self, _: u8, allocs: &mut AllocationConsumer<'_>) -> String {
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match self {
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&AMode::Unscaled(reg, simm9) => {
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let reg = pretty_print_reg(reg, allocs);
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if simm9.value != 0 {
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let simm9 = simm9.pretty_print(8, allocs);
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format!("[{}, {}]", reg, simm9)
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} else {
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format!("[{}]", reg)
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}
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}
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&AMode::UnsignedOffset(reg, uimm12) => {
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let reg = pretty_print_reg(reg, allocs);
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if uimm12.value != 0 {
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let uimm12 = uimm12.pretty_print(8, allocs);
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format!("[{}, {}]", reg, uimm12)
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} else {
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format!("[{}]", reg)
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}
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}
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&AMode::RegReg(r1, r2) => {
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let r1 = pretty_print_reg(r1, allocs);
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let r2 = pretty_print_reg(r2, allocs);
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format!("[{}, {}]", r1, r2)
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}
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&AMode::RegScaled(r1, r2, ty) => {
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let r1 = pretty_print_reg(r1, allocs);
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let r2 = pretty_print_reg(r2, allocs);
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let shift = shift_for_type(ty);
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format!("[{}, {}, LSL #{}]", r1, r2, shift)
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}
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&AMode::RegScaledExtended(r1, r2, ty, op) => {
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let shift = shift_for_type(ty);
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let size = match op {
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ExtendOp::SXTW | ExtendOp::UXTW => OperandSize::Size32,
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_ => OperandSize::Size64,
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};
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let r1 = pretty_print_reg(r1, allocs);
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let r2 = pretty_print_ireg(r2, size, allocs);
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let op = op.pretty_print(0, allocs);
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format!("[{}, {}, {} #{}]", r1, r2, op, shift)
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}
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&AMode::RegExtended(r1, r2, op) => {
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let size = match op {
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ExtendOp::SXTW | ExtendOp::UXTW => OperandSize::Size32,
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_ => OperandSize::Size64,
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};
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let r1 = pretty_print_reg(r1, allocs);
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let r2 = pretty_print_ireg(r2, size, allocs);
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let op = op.pretty_print(0, allocs);
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format!("[{}, {}, {}]", r1, r2, op)
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}
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&AMode::Label(ref label) => label.pretty_print(0, allocs),
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&AMode::PreIndexed(r, simm9) => {
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let r = pretty_print_reg(r.to_reg(), allocs);
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let simm9 = simm9.pretty_print(8, allocs);
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format!("[{}, {}]!", r, simm9)
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}
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&AMode::PostIndexed(r, simm9) => {
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let r = pretty_print_reg(r.to_reg(), allocs);
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let simm9 = simm9.pretty_print(8, allocs);
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format!("[{}], {}", r, simm9)
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}
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// Eliminated by `mem_finalize()`.
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&AMode::SPOffset(..)
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| &AMode::FPOffset(..)
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| &AMode::NominalSPOffset(..)
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| &AMode::RegOffset(..) => {
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panic!("Unexpected pseudo mem-arg mode (stack-offset or generic reg-offset)!")
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}
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}
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}
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}
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impl PrettyPrint for PairAMode {
|
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fn pretty_print(&self, _: u8, allocs: &mut AllocationConsumer<'_>) -> String {
|
|
match self {
|
|
&PairAMode::SignedOffset(reg, simm7) => {
|
|
let reg = pretty_print_reg(reg, allocs);
|
|
if simm7.value != 0 {
|
|
let simm7 = simm7.pretty_print(8, allocs);
|
|
format!("[{}, {}]", reg, simm7)
|
|
} else {
|
|
format!("[{}]", reg)
|
|
}
|
|
}
|
|
&PairAMode::PreIndexed(reg, simm7) => {
|
|
let reg = pretty_print_reg(reg.to_reg(), allocs);
|
|
let simm7 = simm7.pretty_print(8, allocs);
|
|
format!("[{}, {}]!", reg, simm7)
|
|
}
|
|
&PairAMode::PostIndexed(reg, simm7) => {
|
|
let reg = pretty_print_reg(reg.to_reg(), allocs);
|
|
let simm7 = simm7.pretty_print(8, allocs);
|
|
format!("[{}], {}", reg, simm7)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for Cond {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
let mut s = format!("{:?}", self);
|
|
s.make_ascii_lowercase();
|
|
s
|
|
}
|
|
}
|
|
|
|
impl PrettyPrint for BranchTarget {
|
|
fn pretty_print(&self, _: u8, _: &mut AllocationConsumer<'_>) -> String {
|
|
match self {
|
|
&BranchTarget::Label(label) => format!("label{:?}", label.get()),
|
|
&BranchTarget::ResolvedOffset(off) => format!("{}", off),
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Type used to communicate the operand size of a machine instruction, as AArch64 has 32- and
|
|
/// 64-bit variants of many instructions (and integer registers).
|
|
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
|
pub enum OperandSize {
|
|
Size32,
|
|
Size64,
|
|
}
|
|
|
|
impl OperandSize {
|
|
/// 32-bit case?
|
|
pub fn is32(self) -> bool {
|
|
self == OperandSize::Size32
|
|
}
|
|
|
|
/// 64-bit case?
|
|
pub fn is64(self) -> bool {
|
|
self == OperandSize::Size64
|
|
}
|
|
|
|
/// Convert from a needed width to the smallest size that fits.
|
|
pub fn from_bits<I: Into<usize>>(bits: I) -> OperandSize {
|
|
let bits: usize = bits.into();
|
|
assert!(bits <= 64);
|
|
if bits <= 32 {
|
|
OperandSize::Size32
|
|
} else {
|
|
OperandSize::Size64
|
|
}
|
|
}
|
|
|
|
pub fn bits(&self) -> u8 {
|
|
match self {
|
|
OperandSize::Size32 => 32,
|
|
OperandSize::Size64 => 64,
|
|
}
|
|
}
|
|
|
|
/// Convert from an integer type into the smallest size that fits.
|
|
pub fn from_ty(ty: Type) -> OperandSize {
|
|
debug_assert!(!ty.is_vector());
|
|
|
|
Self::from_bits(ty_bits(ty))
|
|
}
|
|
|
|
/// Convert to I32, I64, or I128.
|
|
pub fn to_ty(self) -> Type {
|
|
match self {
|
|
OperandSize::Size32 => I32,
|
|
OperandSize::Size64 => I64,
|
|
}
|
|
}
|
|
|
|
pub fn sf_bit(&self) -> u32 {
|
|
match self {
|
|
OperandSize::Size32 => 0,
|
|
OperandSize::Size64 => 1,
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Type used to communicate the size of a scalar SIMD & FP operand.
|
|
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
|
pub enum ScalarSize {
|
|
Size8,
|
|
Size16,
|
|
Size32,
|
|
Size64,
|
|
Size128,
|
|
}
|
|
|
|
impl ScalarSize {
|
|
/// Convert from a needed width to the smallest size that fits.
|
|
pub fn from_bits<I: Into<usize>>(bits: I) -> ScalarSize {
|
|
match bits.into().next_power_of_two() {
|
|
8 => ScalarSize::Size8,
|
|
16 => ScalarSize::Size16,
|
|
32 => ScalarSize::Size32,
|
|
64 => ScalarSize::Size64,
|
|
128 => ScalarSize::Size128,
|
|
w => panic!("Unexpected type width: {}", w),
|
|
}
|
|
}
|
|
|
|
/// Convert to an integer operand size.
|
|
pub fn operand_size(&self) -> OperandSize {
|
|
match self {
|
|
ScalarSize::Size8 | ScalarSize::Size16 | ScalarSize::Size32 => OperandSize::Size32,
|
|
ScalarSize::Size64 => OperandSize::Size64,
|
|
_ => panic!("Unexpected operand_size request for: {:?}", self),
|
|
}
|
|
}
|
|
|
|
/// Convert from a type into the smallest size that fits.
|
|
pub fn from_ty(ty: Type) -> ScalarSize {
|
|
debug_assert!(!ty.is_vector());
|
|
|
|
Self::from_bits(ty_bits(ty))
|
|
}
|
|
|
|
/// Return the encoding bits that are used by some scalar FP instructions
|
|
/// for a particular operand size.
|
|
pub fn ftype(&self) -> u32 {
|
|
match self {
|
|
ScalarSize::Size16 => 0b11,
|
|
ScalarSize::Size32 => 0b00,
|
|
ScalarSize::Size64 => 0b01,
|
|
_ => panic!("Unexpected scalar FP operand size: {:?}", self),
|
|
}
|
|
}
|
|
|
|
pub fn widen(&self) -> ScalarSize {
|
|
match self {
|
|
ScalarSize::Size8 => ScalarSize::Size16,
|
|
ScalarSize::Size16 => ScalarSize::Size32,
|
|
ScalarSize::Size32 => ScalarSize::Size64,
|
|
ScalarSize::Size64 => ScalarSize::Size128,
|
|
ScalarSize::Size128 => panic!("can't widen 128-bits"),
|
|
}
|
|
}
|
|
|
|
pub fn narrow(&self) -> ScalarSize {
|
|
match self {
|
|
ScalarSize::Size8 => panic!("can't narrow 8-bits"),
|
|
ScalarSize::Size16 => ScalarSize::Size8,
|
|
ScalarSize::Size32 => ScalarSize::Size16,
|
|
ScalarSize::Size64 => ScalarSize::Size32,
|
|
ScalarSize::Size128 => ScalarSize::Size64,
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Type used to communicate the size of a vector operand.
|
|
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
|
pub enum VectorSize {
|
|
Size8x8,
|
|
Size8x16,
|
|
Size16x4,
|
|
Size16x8,
|
|
Size32x2,
|
|
Size32x4,
|
|
Size64x2,
|
|
}
|
|
|
|
impl VectorSize {
|
|
/// Get the vector operand size with the given scalar size as lane size.
|
|
pub fn from_lane_size(size: ScalarSize, is_128bit: bool) -> VectorSize {
|
|
match (size, is_128bit) {
|
|
(ScalarSize::Size8, false) => VectorSize::Size8x8,
|
|
(ScalarSize::Size8, true) => VectorSize::Size8x16,
|
|
(ScalarSize::Size16, false) => VectorSize::Size16x4,
|
|
(ScalarSize::Size16, true) => VectorSize::Size16x8,
|
|
(ScalarSize::Size32, false) => VectorSize::Size32x2,
|
|
(ScalarSize::Size32, true) => VectorSize::Size32x4,
|
|
(ScalarSize::Size64, true) => VectorSize::Size64x2,
|
|
_ => panic!("Unexpected scalar FP operand size: {:?}", size),
|
|
}
|
|
}
|
|
|
|
/// Convert from a type into a vector operand size.
|
|
pub fn from_ty(ty: Type) -> VectorSize {
|
|
debug_assert!(ty.is_vector());
|
|
|
|
match ty {
|
|
B8X8 => VectorSize::Size8x8,
|
|
B8X16 => VectorSize::Size8x16,
|
|
B16X4 => VectorSize::Size16x4,
|
|
B16X8 => VectorSize::Size16x8,
|
|
B32X2 => VectorSize::Size32x2,
|
|
B32X4 => VectorSize::Size32x4,
|
|
B64X2 => VectorSize::Size64x2,
|
|
F32X2 => VectorSize::Size32x2,
|
|
F32X4 => VectorSize::Size32x4,
|
|
F64X2 => VectorSize::Size64x2,
|
|
I8X8 => VectorSize::Size8x8,
|
|
I8X16 => VectorSize::Size8x16,
|
|
I16X4 => VectorSize::Size16x4,
|
|
I16X8 => VectorSize::Size16x8,
|
|
I32X2 => VectorSize::Size32x2,
|
|
I32X4 => VectorSize::Size32x4,
|
|
I64X2 => VectorSize::Size64x2,
|
|
_ => unimplemented!("Unsupported type: {}", ty),
|
|
}
|
|
}
|
|
|
|
/// Get the integer operand size that corresponds to a lane of a vector with a certain size.
|
|
pub fn operand_size(&self) -> OperandSize {
|
|
match self {
|
|
VectorSize::Size64x2 => OperandSize::Size64,
|
|
_ => OperandSize::Size32,
|
|
}
|
|
}
|
|
|
|
/// Get the scalar operand size that corresponds to a lane of a vector with a certain size.
|
|
pub fn lane_size(&self) -> ScalarSize {
|
|
match self {
|
|
VectorSize::Size8x8 | VectorSize::Size8x16 => ScalarSize::Size8,
|
|
VectorSize::Size16x4 | VectorSize::Size16x8 => ScalarSize::Size16,
|
|
VectorSize::Size32x2 | VectorSize::Size32x4 => ScalarSize::Size32,
|
|
VectorSize::Size64x2 => ScalarSize::Size64,
|
|
}
|
|
}
|
|
|
|
pub fn is_128bits(&self) -> bool {
|
|
match self {
|
|
VectorSize::Size8x8 => false,
|
|
VectorSize::Size8x16 => true,
|
|
VectorSize::Size16x4 => false,
|
|
VectorSize::Size16x8 => true,
|
|
VectorSize::Size32x2 => false,
|
|
VectorSize::Size32x4 => true,
|
|
VectorSize::Size64x2 => true,
|
|
}
|
|
}
|
|
|
|
/// Return the encoding bits that are used by some SIMD instructions
|
|
/// for a particular operand size.
|
|
pub fn enc_size(&self) -> (u32, u32) {
|
|
let q = self.is_128bits() as u32;
|
|
let size = match self.lane_size() {
|
|
ScalarSize::Size8 => 0b00,
|
|
ScalarSize::Size16 => 0b01,
|
|
ScalarSize::Size32 => 0b10,
|
|
ScalarSize::Size64 => 0b11,
|
|
_ => unreachable!(),
|
|
};
|
|
|
|
(q, size)
|
|
}
|
|
|
|
/// Return the encoding bit that is used by some floating-point SIMD
|
|
/// instructions for a particular operand size.
|
|
pub fn enc_float_size(&self) -> u32 {
|
|
match self.lane_size() {
|
|
ScalarSize::Size32 => 0b0,
|
|
ScalarSize::Size64 => 0b1,
|
|
size => panic!("Unsupported floating-point size for vector op: {:?}", size),
|
|
}
|
|
}
|
|
}
|