Jakob Stoklund Olesen 4ee519e620 Add RISC-V call instruction encodings. ...

Calls are jal with a fixed %x1 link register.

2017-04-11 10:40:38 -07:00

..

arm32

Add a section about implementation limits.

2017-02-24 11:08:15 -08:00

arm64

Generate register class descriptors.

2017-01-20 14:23:06 -08:00

intel

Generate register class descriptors.

2017-01-20 14:23:06 -08:00

riscv

Add RISC-V call instruction encodings.

2017-04-11 10:40:38 -07:00

__init__.py

Fixed for mypy 0.501.

2017-03-03 09:08:28 -08:00