e4dc9c7944
* Update Intel x86 CPU presets * Add LLVM reference * Remove 32bit CPU architectures * Rename silvermont to slm * Fix haswell presets * Add icelake alias * Group streaming simd presets * Add slm silvermont preset * Remove duplicate alderlake def
354 lines
11 KiB
Rust
354 lines
11 KiB
Rust
use crate::cdsl::isa::TargetIsa;
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use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
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use crate::shared::Definitions as SharedDefinitions;
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pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
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let settings = define_settings(&shared_defs.settings);
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TargetIsa::new("x86", settings)
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}
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fn define_settings(shared: &SettingGroup) -> SettingGroup {
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let mut settings = SettingGroupBuilder::new("x86");
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// CPUID.01H:ECX
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let has_sse3 = settings.add_bool(
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"has_sse3",
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"Has support for SSE3.",
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"SSE3: CPUID.01H:ECX.SSE3[bit 0]",
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// Needed for default `enable_simd` setting.
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true,
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);
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let has_ssse3 = settings.add_bool(
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"has_ssse3",
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"Has support for SSSE3.",
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"SSSE3: CPUID.01H:ECX.SSSE3[bit 9]",
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// Needed for default `enable_simd` setting.
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true,
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);
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let has_sse41 = settings.add_bool(
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"has_sse41",
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"Has support for SSE4.1.",
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"SSE4.1: CPUID.01H:ECX.SSE4_1[bit 19]",
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// Needed for default `enable_simd` setting.
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true,
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);
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let has_sse42 = settings.add_bool(
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"has_sse42",
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"Has support for SSE4.2.",
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"SSE4.2: CPUID.01H:ECX.SSE4_2[bit 20]",
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true,
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);
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let has_avx = settings.add_bool(
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"has_avx",
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"Has support for AVX.",
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"AVX: CPUID.01H:ECX.AVX[bit 28]",
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false,
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);
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let has_avx2 = settings.add_bool(
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"has_avx2",
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"Has support for AVX2.",
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"AVX2: CPUID.07H:EBX.AVX2[bit 5]",
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false,
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);
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let has_fma = settings.add_bool(
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"has_fma",
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"Has support for FMA.",
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"FMA: CPUID.01H:ECX.FMA[bit 12]",
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false,
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);
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let has_avx512bitalg = settings.add_bool(
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"has_avx512bitalg",
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"Has support for AVX512BITALG.",
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"AVX512BITALG: CPUID.07H:ECX.AVX512BITALG[bit 12]",
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false,
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);
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let has_avx512dq = settings.add_bool(
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"has_avx512dq",
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"Has support for AVX512DQ.",
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"AVX512DQ: CPUID.07H:EBX.AVX512DQ[bit 17]",
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false,
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);
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let has_avx512vl = settings.add_bool(
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"has_avx512vl",
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"Has support for AVX512VL.",
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"AVX512VL: CPUID.07H:EBX.AVX512VL[bit 31]",
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false,
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);
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let has_avx512vbmi = settings.add_bool(
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"has_avx512vbmi",
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"Has support for AVX512VMBI.",
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"AVX512VBMI: CPUID.07H:ECX.AVX512VBMI[bit 1]",
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false,
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);
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let has_avx512f = settings.add_bool(
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"has_avx512f",
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"Has support for AVX512F.",
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"AVX512F: CPUID.07H:EBX.AVX512F[bit 16]",
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false,
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);
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let has_popcnt = settings.add_bool(
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"has_popcnt",
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"Has support for POPCNT.",
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"POPCNT: CPUID.01H:ECX.POPCNT[bit 23]",
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false,
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);
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// CPUID.(EAX=07H, ECX=0H):EBX
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let has_bmi1 = settings.add_bool(
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"has_bmi1",
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"Has support for BMI1.",
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"BMI1: CPUID.(EAX=07H, ECX=0H):EBX.BMI1[bit 3]",
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false,
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);
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let has_bmi2 = settings.add_bool(
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"has_bmi2",
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"Has support for BMI2.",
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"BMI2: CPUID.(EAX=07H, ECX=0H):EBX.BMI2[bit 8]",
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false,
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);
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// CPUID.EAX=80000001H:ECX
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let has_lzcnt = settings.add_bool(
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"has_lzcnt",
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"Has support for LZCNT.",
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"LZCNT: CPUID.EAX=80000001H:ECX.LZCNT[bit 5]",
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false,
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);
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let shared_enable_simd = shared.get_bool("enable_simd");
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settings.add_predicate("use_ssse3", predicate!(has_ssse3));
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settings.add_predicate("use_sse41", predicate!(has_sse41));
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settings.add_predicate("use_sse42", predicate!(has_sse41 && has_sse42));
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settings.add_predicate("use_fma", predicate!(has_avx && has_fma));
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settings.add_predicate(
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"use_ssse3_simd",
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predicate!(shared_enable_simd && has_ssse3),
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);
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settings.add_predicate(
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"use_sse41_simd",
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predicate!(shared_enable_simd && has_sse41),
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);
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settings.add_predicate(
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"use_sse42_simd",
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predicate!(shared_enable_simd && has_sse41 && has_sse42),
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);
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settings.add_predicate("use_avx_simd", predicate!(shared_enable_simd && has_avx));
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settings.add_predicate("use_avx2_simd", predicate!(shared_enable_simd && has_avx2));
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settings.add_predicate(
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"use_avx512bitalg_simd",
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predicate!(shared_enable_simd && has_avx512bitalg),
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);
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settings.add_predicate(
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"use_avx512dq_simd",
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predicate!(shared_enable_simd && has_avx512dq),
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);
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settings.add_predicate(
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"use_avx512vl_simd",
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predicate!(shared_enable_simd && has_avx512vl),
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);
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settings.add_predicate(
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"use_avx512vbmi_simd",
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predicate!(shared_enable_simd && has_avx512vbmi),
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);
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settings.add_predicate(
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"use_avx512f_simd",
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predicate!(shared_enable_simd && has_avx512f),
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);
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settings.add_predicate("use_popcnt", predicate!(has_popcnt && has_sse42));
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settings.add_predicate("use_bmi1", predicate!(has_bmi1));
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settings.add_predicate("use_lzcnt", predicate!(has_lzcnt));
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let sse3 = settings.add_preset("sse3", "SSE3 and earlier.", preset!(has_sse3));
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let ssse3 = settings.add_preset("ssse3", "SSSE3 and earlier.", preset!(sse3 && has_ssse3));
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let sse41 = settings.add_preset("sse41", "SSE4.1 and earlier.", preset!(ssse3 && has_sse41));
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let sse42 = settings.add_preset("sse42", "SSE4.2 and earlier.", preset!(sse41 && has_sse42));
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// Presets corresponding to x86 CPUs.
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// Features and architecture names are from LLVM's x86 presets:
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// https://github.com/llvm/llvm-project/blob/d4493dd1ed58ac3f1eab0c4ca6e363e2b15bfd1c/llvm/lib/Target/X86/X86.td#L1300-L1643
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settings.add_preset(
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"baseline",
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"A baseline preset with no extensions enabled.",
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preset!(),
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);
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// Intel CPUs
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// Netburst
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settings.add_preset("nocona", "Nocona microarchitecture.", preset!(sse3));
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// Intel Core 2 Solo/Duo
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settings.add_preset("core2", "Core 2 microarchitecture.", preset!(sse3));
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settings.add_preset("penryn", "Penryn microarchitecture.", preset!(sse41));
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// Intel Atom CPUs
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let atom = settings.add_preset("atom", "Atom microarchitecture.", preset!(ssse3));
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settings.add_preset("bonnell", "Bonnell microarchitecture.", preset!(atom));
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let silvermont = settings.add_preset(
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"silvermont",
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"Silvermont microarchitecture.",
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preset!(atom && sse42 && has_popcnt),
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);
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settings.add_preset("slm", "Silvermont microarchitecture.", preset!(silvermont));
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let goldmont = settings.add_preset(
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"goldmont",
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"Goldmont microarchitecture.",
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preset!(silvermont),
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);
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settings.add_preset(
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"goldmont-plus",
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"Goldmont Plus microarchitecture.",
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preset!(goldmont),
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);
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let tremont = settings.add_preset("tremont", "Tremont microarchitecture.", preset!(goldmont));
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let alderlake = settings.add_preset(
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"alderlake",
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"Alderlake microarchitecture.",
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preset!(tremont && has_bmi1 && has_bmi2 && has_lzcnt && has_fma),
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);
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let sierra_forest = settings.add_preset(
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"sierraforest",
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"Sierra Forest microarchitecture.",
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preset!(alderlake),
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);
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settings.add_preset(
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"grandridge",
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"Grandridge microarchitecture.",
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preset!(sierra_forest),
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);
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let nehalem = settings.add_preset(
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"nehalem",
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"Nehalem microarchitecture.",
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preset!(sse42 && has_popcnt),
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);
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settings.add_preset("corei7", "Core i7 microarchitecture.", preset!(nehalem));
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let westmere = settings.add_preset("westmere", "Westmere microarchitecture.", preset!(nehalem));
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let sandy_bridge = settings.add_preset(
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"sandybridge",
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"Sandy Bridge microarchitecture.",
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preset!(westmere && has_avx),
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);
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settings.add_preset(
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"corei7-avx",
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"Core i7 AVX microarchitecture.",
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preset!(sandy_bridge),
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);
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let ivy_bridge = settings.add_preset(
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"ivybridge",
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"Ivy Bridge microarchitecture.",
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preset!(sandy_bridge),
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);
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settings.add_preset(
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"core-avx-i",
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"Intel Core CPU with 64-bit extensions.",
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preset!(ivy_bridge),
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);
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let haswell = settings.add_preset(
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"haswell",
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"Haswell microarchitecture.",
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preset!(ivy_bridge && has_avx2 && has_bmi1 && has_bmi2 && has_fma && has_lzcnt),
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);
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settings.add_preset(
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"core-avx2",
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"Intel Core CPU with AVX2 extensions.",
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preset!(haswell),
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);
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let broadwell = settings.add_preset(
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"broadwell",
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"Broadwell microarchitecture.",
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preset!(haswell),
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);
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let skylake = settings.add_preset("skylake", "Skylake microarchitecture.", preset!(broadwell));
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let knights_landing = settings.add_preset(
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"knl",
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"Knights Landing microarchitecture.",
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preset!(has_popcnt && has_avx512f && has_fma && has_bmi1 && has_bmi2 && has_lzcnt),
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);
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settings.add_preset(
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"knm",
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"Knights Mill microarchitecture.",
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preset!(knights_landing),
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);
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let skylake_avx512 = settings.add_preset(
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"skylake-avx512",
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"Skylake AVX512 microarchitecture.",
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preset!(broadwell && has_avx512f && has_avx512dq && has_avx512vl),
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);
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settings.add_preset(
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"skx",
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"Skylake AVX512 microarchitecture.",
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preset!(skylake_avx512),
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);
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let cascadelake = settings.add_preset(
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"cascadelake",
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"Cascade Lake microarchitecture.",
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preset!(skylake_avx512),
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);
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settings.add_preset(
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"cooperlake",
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"Cooper Lake mircoarchitecture.",
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preset!(cascadelake),
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);
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let cannonlake = settings.add_preset(
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"cannonlake",
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"Canon Lake microarchitecture.",
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preset!(skylake && has_avx512f && has_avx512dq && has_avx512vl && has_avx512vbmi),
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);
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let icelake_client = settings.add_preset(
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"icelake-client",
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"Ice Lake microarchitecture.",
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preset!(cannonlake && has_avx512bitalg),
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);
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// LLVM doesn't use the name "icelake" but Cranelift did in the past; alias it
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settings.add_preset(
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"icelake",
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"Ice Lake microarchitecture",
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preset!(icelake_client),
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);
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let icelake_server = settings.add_preset(
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"icelake-server",
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"Ice Lake (server) microarchitecture.",
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preset!(icelake_client),
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);
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settings.add_preset(
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"tigerlake",
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"Tiger Lake microarchitecture.",
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preset!(icelake_client),
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);
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let sapphire_rapids = settings.add_preset(
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"sapphirerapids",
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"Saphire Rapids microarchitecture.",
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preset!(icelake_server),
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);
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settings.add_preset(
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"raptorlake",
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"Raptor Lake microarchitecture.",
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preset!(alderlake),
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);
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settings.add_preset(
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"meteorlake",
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"Meteor Lake microarchitecture.",
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preset!(alderlake),
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);
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settings.add_preset(
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"graniterapids",
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"Granite Rapids microarchitecture.",
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preset!(sapphire_rapids),
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);
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settings.add_preset(
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"znver1",
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"Zen (first generation) microarchitecture.",
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preset!(sse42 && has_popcnt && has_bmi1 && has_bmi2 && has_lzcnt),
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);
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settings.build()
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}
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