43a86f14d5
This also paves the way for unifying TargetIsa and MachBackend, since now they map one to one. In theory the two traits could be merged, which would be nice to limit the number of total concepts. Also they have quite different responsibilities, so it might be fine to keep them separate. Interestingly, this PR started as removing RegInfo from the TargetIsa trait since the adapter returned a dummy value there. From the fallout, noticed that all Display implementations didn't needed an ISA anymore (since these were only used to render ISA specific registers). Also the whole family of RegInfo / ValueLoc / RegUnit was exclusively used for the old backend, and these could be removed. Notably, some IR instructions needed to be removed, because they were using RegUnit too: this was the oddball of regfill / regmove / regspill / copy_special, which were IR instructions inserted by the old regalloc. Fare thee well!
92 lines
1.5 KiB
Plaintext
92 lines
1.5 KiB
Plaintext
test licm
|
|
target riscv32
|
|
|
|
function %other_side_effects(i32) -> i32 {
|
|
|
|
block0(v0: i32):
|
|
jump block1(v0)
|
|
|
|
block1(v1: i32):
|
|
v2 = iconst.i32 1
|
|
brz v1, block3(v1)
|
|
jump block2
|
|
|
|
block2:
|
|
v5 = isub v1, v2
|
|
jump block1(v5)
|
|
|
|
block3(v6: i32):
|
|
return v6
|
|
|
|
}
|
|
|
|
function %cpu_flags(i32, i32) -> i32 {
|
|
block0(v0: i32, v1: i32):
|
|
jump block1(v0, v1)
|
|
|
|
block1(v2: i32, v3: i32):
|
|
v4 = ifcmp.i32 v0, v1
|
|
v5 = selectif.i32 eq v4, v2, v3
|
|
; check: block1(v2: i32, v3: i32):
|
|
; check: ifcmp.i32 v0, v1
|
|
; check: v5 = selectif.i32 eq v4, v2, v3
|
|
v8 = iconst.i32 1
|
|
brz v1, block3(v1)
|
|
jump block2
|
|
|
|
block2:
|
|
v9 = isub v1, v8
|
|
v10 = iadd v1, v8
|
|
jump block1(v9, v10)
|
|
|
|
block3(v6: i32):
|
|
return v6
|
|
}
|
|
|
|
function %spill(i32, i32) -> i32 {
|
|
block0(v0: i32, v1: i32):
|
|
v2 = spill.i32 v0
|
|
jump block1(v0, v1)
|
|
|
|
block1(v3: i32, v4: i32):
|
|
v5 = spill.i32 v1
|
|
v6 = fill.i32 v2
|
|
v7 = fill.i32 v5
|
|
; check: block1(v3: i32, v4: i32):
|
|
; check: v5 = spill.i32 v1
|
|
; check: v6 = fill.i32 v2
|
|
; check: v7 = fill v5
|
|
brz v1, block3(v1)
|
|
jump block2
|
|
|
|
block2:
|
|
v9 = isub v1, v4
|
|
jump block1(v9, v3)
|
|
|
|
block3(v10: i32):
|
|
return v10
|
|
}
|
|
|
|
function %non_invariant_aliases(i32) -> i32 {
|
|
|
|
block0(v0: i32):
|
|
jump block1(v0)
|
|
|
|
block1(v1: i32):
|
|
v8 -> v1
|
|
v9 -> v1
|
|
v2 = iadd v8, v9
|
|
; check: block1(v1: i32):
|
|
; check: v2 = iadd v8, v9
|
|
brz v1, block3(v1)
|
|
jump block2
|
|
|
|
block2:
|
|
v5 = isub v1, v2
|
|
jump block1(v5)
|
|
|
|
block3(v6: i32):
|
|
return v6
|
|
|
|
}
|