ebf5c80959
The following instructions have simple encodings: - bitcast.f32.i32 - bitcast.i32.f32 - bitcast.f64.i64 - bitcast.i64.f64 - fpromote.f64.f32 - fdemote.f32.f64 Also add helper functions enc_flt() and enc_i32_i64 to intel.encodings.py for generating the common set of encodings for an instruction: I32, I64 w/REX, I64 w/o REX.
147 lines
5.6 KiB
Plaintext
147 lines
5.6 KiB
Plaintext
; Binary emission of 32-bit floating point code.
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test binemit
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isa intel has_sse2
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; The binary encodings can be verified with the command:
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;
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; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary32-float.cton | llvm-mc -show-encoding -triple=i386
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;
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function %F32() {
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ebb0:
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[-,%rcx] v0 = iconst.i32 1
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[-,%rsi] v1 = iconst.i32 2
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; asm: cvtsi2ss %ecx, %xmm5
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[-,%xmm5] v10 = fcvt_from_sint.f32 v0 ; bin: f3 0f 2a e9
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; asm: cvtsi2ss %esi, %xmm2
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[-,%xmm2] v11 = fcvt_from_sint.f32 v1 ; bin: f3 0f 2a d6
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; asm: cvtss2sd %xmm2, %xmm5
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[-,%xmm5] v12 = fpromote.f64 v11 ; bin: f3 0f 5a ea
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; asm: cvtss2sd %xmm5, %xmm2
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[-,%xmm2] v13 = fpromote.f64 v10 ; bin: f3 0f 5a d5
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; asm: movd %ecx, %xmm5
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[-,%xmm5] v14 = bitcast.f32 v0 ; bin: 66 0f 6e e9
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; asm: movd %esi, %xmm2
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[-,%xmm2] v15 = bitcast.f32 v1 ; bin: 66 0f 6e d6
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; asm: movd %xmm5, %ecx
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[-,%rcx] v16 = bitcast.i32 v10 ; bin: 66 0f 7e e9
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; asm: movd %xmm2, %esi
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[-,%rsi] v17 = bitcast.i32 v11 ; bin: 66 0f 7e d6
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; Binary arithmetic.
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; asm: addss %xmm2, %xmm5
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[-,%xmm5] v20 = fadd v10, v11 ; bin: f3 0f 58 ea
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; asm: addss %xmm5, %xmm2
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[-,%xmm2] v21 = fadd v11, v10 ; bin: f3 0f 58 d5
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; asm: subss %xmm2, %xmm5
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[-,%xmm5] v22 = fsub v10, v11 ; bin: f3 0f 5c ea
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; asm: subss %xmm5, %xmm2
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[-,%xmm2] v23 = fsub v11, v10 ; bin: f3 0f 5c d5
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; asm: mulss %xmm2, %xmm5
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[-,%xmm5] v24 = fmul v10, v11 ; bin: f3 0f 59 ea
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; asm: mulss %xmm5, %xmm2
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[-,%xmm2] v25 = fmul v11, v10 ; bin: f3 0f 59 d5
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; asm: divss %xmm2, %xmm5
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[-,%xmm5] v26 = fdiv v10, v11 ; bin: f3 0f 5e ea
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; asm: divss %xmm5, %xmm2
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[-,%xmm2] v27 = fdiv v11, v10 ; bin: f3 0f 5e d5
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; Bitwise ops.
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; We use the *ps SSE instructions for everything because they are smaller.
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; asm: andps %xmm2, %xmm5
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[-,%xmm5] v30 = band v10, v11 ; bin: 0f 54 ea
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; asm: andps %xmm5, %xmm2
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[-,%xmm2] v31 = band v11, v10 ; bin: 0f 54 d5
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; asm: andnps %xmm2, %xmm5
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[-,%xmm5] v32 = band_not v10, v11 ; bin: 0f 55 ea
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; asm: andnps %xmm5, %xmm2
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[-,%xmm2] v33 = band_not v11, v10 ; bin: 0f 55 d5
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; asm: orps %xmm2, %xmm5
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[-,%xmm5] v34 = bor v10, v11 ; bin: 0f 56 ea
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; asm: orps %xmm5, %xmm2
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[-,%xmm2] v35 = bor v11, v10 ; bin: 0f 56 d5
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; asm: xorps %xmm2, %xmm5
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[-,%xmm5] v36 = bxor v10, v11 ; bin: 0f 57 ea
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; asm: xorps %xmm5, %xmm2
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[-,%xmm2] v37 = bxor v11, v10 ; bin: 0f 57 d5
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return
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}
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function %F64() {
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ebb0:
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[-,%rcx] v0 = iconst.i32 1
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[-,%rsi] v1 = iconst.i32 2
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; asm: cvtsi2sd %ecx, %xmm5
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[-,%xmm5] v10 = fcvt_from_sint.f64 v0 ; bin: f2 0f 2a e9
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; asm: cvtsi2sd %esi, %xmm2
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[-,%xmm2] v11 = fcvt_from_sint.f64 v1 ; bin: f2 0f 2a d6
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; asm: cvtsd2ss %xmm2, %xmm5
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[-,%xmm5] v12 = fdemote.f32 v11 ; bin: f2 0f 5a ea
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; asm: cvtsd2ss %xmm5, %xmm2
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[-,%xmm2] v13 = fdemote.f32 v10 ; bin: f2 0f 5a d5
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; No i64 <-> f64 bitcasts in 32-bit mode.
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; Binary arithmetic.
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; asm: addsd %xmm2, %xmm5
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[-,%xmm5] v20 = fadd v10, v11 ; bin: f2 0f 58 ea
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; asm: addsd %xmm5, %xmm2
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[-,%xmm2] v21 = fadd v11, v10 ; bin: f2 0f 58 d5
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; asm: subsd %xmm2, %xmm5
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[-,%xmm5] v22 = fsub v10, v11 ; bin: f2 0f 5c ea
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; asm: subsd %xmm5, %xmm2
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[-,%xmm2] v23 = fsub v11, v10 ; bin: f2 0f 5c d5
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; asm: mulsd %xmm2, %xmm5
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[-,%xmm5] v24 = fmul v10, v11 ; bin: f2 0f 59 ea
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; asm: mulsd %xmm5, %xmm2
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[-,%xmm2] v25 = fmul v11, v10 ; bin: f2 0f 59 d5
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; asm: divsd %xmm2, %xmm5
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[-,%xmm5] v26 = fdiv v10, v11 ; bin: f2 0f 5e ea
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; asm: divsd %xmm5, %xmm2
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[-,%xmm2] v27 = fdiv v11, v10 ; bin: f2 0f 5e d5
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; Bitwise ops.
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; We use the *ps SSE instructions for everything because they are smaller.
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; asm: andps %xmm2, %xmm5
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[-,%xmm5] v30 = band v10, v11 ; bin: 0f 54 ea
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; asm: andps %xmm5, %xmm2
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[-,%xmm2] v31 = band v11, v10 ; bin: 0f 54 d5
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; asm: andnps %xmm2, %xmm5
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[-,%xmm5] v32 = band_not v10, v11 ; bin: 0f 55 ea
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; asm: andnps %xmm5, %xmm2
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[-,%xmm2] v33 = band_not v11, v10 ; bin: 0f 55 d5
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; asm: orps %xmm2, %xmm5
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[-,%xmm5] v34 = bor v10, v11 ; bin: 0f 56 ea
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; asm: orps %xmm5, %xmm2
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[-,%xmm2] v35 = bor v11, v10 ; bin: 0f 56 d5
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; asm: xorps %xmm2, %xmm5
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[-,%xmm5] v36 = bxor v10, v11 ; bin: 0f 57 ea
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; asm: xorps %xmm5, %xmm2
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[-,%xmm2] v37 = bxor v11, v10 ; bin: 0f 57 d5
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return
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}
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