f59b274d22
Introduce support for MOVI/MVNI with 16-, 32-, and 64-bit elements, and the vector variant of FMOV. Copyright (c) 2020, Arm Limited.
173 lines
3.3 KiB
Plaintext
173 lines
3.3 KiB
Plaintext
test compile
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target aarch64
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function %f1() -> i64x2 {
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block0:
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v0 = iconst.i64 281474976710657
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v1 = splat.i64x2 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x0, #1
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; nextln: movk x0, #1, LSL #48
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; nextln: dup v0.2d, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f2() -> i16x8 {
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block0:
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v0 = iconst.i32 42679
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v1 = ireduce.i16 v0
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v2 = splat.i16x8 v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x0, #42679
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; nextln: dup v0.8h, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f3() -> b8x16 {
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block0:
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v0 = bconst.b32 true
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v1 = breduce.b8 v0
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v2 = splat.b8x16 v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movi v0.16b, #255
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f4(i32, i8x16, i8x16) -> i8x16 {
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block0(v0: i32, v1: i8x16, v2: i8x16):
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v3 = select v0, v1, v2
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return v3
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: subs wzr, w0, wzr
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; nextln: vcsel v0.16b, v0.16b, v1.16b, ne (if-then-else diamond)
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f5(i64) -> i8x16 {
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block0(v0: i64):
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v1 = load.i8 v0
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v2 = splat.i8x16 v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ld1r { v0.16b }, [x0]
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f6(i64, i64) -> i8x16, i8x16 {
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block0(v0: i64, v1: i64):
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v2 = load.i8 v0
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v3 = load.i8 v1
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v4 = splat.i8x16 v2
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v5 = splat.i8x16 v3
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return v4, v5
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ld1r { v0.16b }, [x0]
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; nextln: ld1r { v1.16b }, [x1]
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f7(i64, i64) -> i8x16, i8x16 {
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block0(v0: i64, v1: i64):
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v2 = load.i8 v0
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v3 = load.i8 v1
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v4 = splat.i8x16 v3
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v5 = splat.i8x16 v2
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return v4, v5
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ldrb w0, [x0]
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; nextln: ld1r { v0.16b }, [x1]
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; nextln: dup v1.16b, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f8(i64, i64) -> i8x16, i8x16 {
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block0(v0: i64, v1: i64):
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v2 = load.i8 v0
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v3 = splat.i8x16 v2
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v4 = splat.i8x16 v2
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return v3, v4
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ldrb w0, [x0]
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; nextln: dup v0.16b, w0
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; nextln: dup v1.16b, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f9() -> i32x2 {
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block0:
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v0 = iconst.i32 4278190335
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v1 = splat.i32x2 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movi v0.2d, #18374687579166474495
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; nextln: fmov d0, d0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f10() -> i32x4 {
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block0:
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v0 = iconst.i32 4293918720
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v1 = splat.i32x4 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mvni v0.4s, #15, MSL #16
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f11() -> f32x4 {
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block0:
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v0 = f32const 0x1.5
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v1 = splat.f32x4 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: fmov v0.4s, #1.3125
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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