cb48ea406e
This PR switches the default backend on x86, for both the `cranelift-codegen` crate and for Wasmtime, to the new (`MachInst`-style, `VCode`-based) backend that has been under development and testing for some time now. The old backend is still available by default in builds with the `old-x86-backend` feature, or by requesting `BackendVariant::Legacy` from the appropriate APIs. As part of that switch, it adds some more runtime-configurable plumbing to the testing infrastructure so that tests can be run using the appropriate backend. `clif-util test` is now capable of parsing a backend selector option from filetests and instantiating the correct backend. CI has been updated so that the old x86 backend continues to run its tests, just as we used to run the new x64 backend separately. At some point, we will remove the old x86 backend entirely, once we are satisfied that the new backend has not caused any unforeseen issues and we do not need to revert.
280 lines
6.2 KiB
Plaintext
280 lines
6.2 KiB
Plaintext
test run
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set enable_simd
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target x86_64 machinst skylake
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function %iadd_i32x4(i32x4, i32x4) -> i32x4 {
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block0(v0:i32x4, v1:i32x4):
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v2 = iadd v0, v1
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return v2
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}
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; run: %iadd_i32x4([1 1 1 1], [1 2 3 4]) == [2 3 4 5]
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function %iadd_i8x16_with_overflow() -> i8x16 {
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block0:
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v0 = vconst.i8x16 [255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255]
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v1 = vconst.i8x16 [2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2]
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v2 = iadd v0, v1
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return v2
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}
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; run: %iadd_i8x16_with_overflow() == [1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1]
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function %isub_i32x4_rex() -> b1 {
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block0:
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v0 = vconst.i32x4 [1 1 1 1]
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v1 = vconst.i32x4 [1 2 3 4]
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v2 = isub v0, v1
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v3 = extractlane v2, 0
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v4 = icmp_imm eq v3, 0
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v5 = extractlane v2, 1
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v6 = icmp_imm eq v5, 0xffffffff
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; TODO replace extractlanes with vector comparison
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v7 = band v4, v6
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return v7
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}
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; run
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function %ineg_i32x4() -> b1 {
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block0:
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v0 = vconst.i32x4 [1 1 1 1]
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v2 = ineg v0
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v3 = extractlane v2, 0
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v4 = icmp_imm eq v3, -1
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return v4
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}
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; run
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function %imul_i64x2(i64x2, i64x2) -> i64x2 {
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block0(v0: i64x2, v1: i64x2):
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v2 = imul v0, v1
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return v2
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}
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; run: %imul_i64x2([0 2], [0 2]) == [0 4]
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function %imul_i32x4() -> b1 {
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block0:
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v0 = vconst.i32x4 [-1 0 1 0x80_00_00_01]
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v1 = vconst.i32x4 [2 2 2 2]
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v2 = imul v0, v1
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v3 = extractlane v2, 0
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v4 = icmp_imm eq v3, -2
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v5 = extractlane v2, 1
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v6 = icmp_imm eq v5, 0
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v7 = extractlane v2, 3
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v8 = icmp_imm eq v7, 2 ; 0x80_00_00_01 * 2 == 0x1_00_00_00_02 (and the 1 is dropped)
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v9 = band v4, v6
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v10 = band v8, v9
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return v10
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}
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; run
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function %imul_i16x8() -> b1 {
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block0:
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v0 = vconst.i16x8 [-1 0 1 0x7f_ff 0 0 0 0]
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v1 = vconst.i16x8 [2 2 2 2 0 0 0 0]
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v2 = imul v0, v1
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v3 = extractlane v2, 0
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v4 = icmp_imm eq v3, 0xfffe ; 0xfffe == -2; -2 will not work here and below because v3 is
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; being uextend-ed, not sextend-ed
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v5 = extractlane v2, 1
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v6 = icmp_imm eq v5, 0
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v7 = extractlane v2, 3
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v8 = icmp_imm eq v7, 0xfffe ; 0x7f_ff * 2 == 0xff_fe
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v9 = band v4, v6
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v10 = band v8, v9
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return v4
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}
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; run
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function %sadd_sat_i8x16() -> b1 {
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block0:
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v0 = vconst.i8x16 [127 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0]
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v1 = vconst.i8x16 [1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1]
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v2 = sadd_sat v0, v1
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v3 = extractlane v2, 0
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v4 = icmp_imm eq v3, 127
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return v4
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}
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; run
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function %uadd_sat_i16x8() -> b1 {
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block0:
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v0 = vconst.i16x8 [-1 0 0 0 0 0 0 0]
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v1 = vconst.i16x8 [-1 1 1 1 1 1 1 1]
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v2 = uadd_sat v0, v1
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v3 = extractlane v2, 0
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v4 = icmp_imm eq v3, 65535
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return v4
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}
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; run
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function %sub_sat_i8x16() -> b1 {
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block0:
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v0 = vconst.i8x16 [128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0] ; 128 == 0x80 == -128
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v1 = vconst.i8x16 [1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1]
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v2 = ssub_sat v0, v1
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v3 = extractlane v2, 0
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v4 = icmp_imm eq v3, 0x80 ; 0x80 == -128
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; now re-use 0x80 as an unsigned 128
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v5 = usub_sat v0, v2
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v6 = extractlane v5, 0
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v7 = icmp_imm eq v6, 0
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v8 = band v4, v7
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return v8
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}
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; run
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;function %add_sub_f32x4() -> b1 {
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;block0:
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; v0 = vconst.f32x4 [0x4.2 0.0 0.0 0.0]
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; v1 = vconst.f32x4 [0x1.0 0x1.0 0x1.0 0x1.0]
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; v2 = vconst.f32x4 [0x5.2 0x1.0 0x1.0 0x1.0]
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;
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; v3 = fadd v0, v1
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; v4 = fcmp eq v3, v2
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;
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; v6 = fsub v2, v1
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; v7 = fcmp eq v6, v0
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;
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; v8 = band v4, v7
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; v9 = vall_true v8
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; return v9
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;}
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; _run
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;function %mul_div_f32x4() -> b1 {
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;block0:
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; v0 = vconst.f32x4 [0x4.2 -0x2.1 0x2.0 0.0]
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; v1 = vconst.f32x4 [0x3.4 0x6.7 0x8.9 0xa.b]
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; v2 = vconst.f32x4 [0xd.68 -0xd.47 0x11.2 0x0.0]
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;
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; v3 = fmul v0, v1
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; v4 = fcmp eq v3, v2
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;
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; v6 = fdiv v2, v1
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; v7 = fcmp eq v6, v0
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;
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; v8 = band v4, v7
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; v9 = vall_true v8
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; return v9
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;}
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; _run
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;function %sqrt_f64x2() -> b1 {
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;block0:
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; v0 = vconst.f64x2 [0x9.0 0x1.0]
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; v1 = sqrt v0
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; v2 = vconst.f64x2 [0x3.0 0x1.0]
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; v3 = fcmp eq v2, v1
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; v4 = vall_true v3
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; return v4
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;}
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; _run
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function %fmax_f64x2(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = fmax v0, v1
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return v2
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}
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; note below how NaNs are quieted but (unlike fmin), retain their sign: this discrepancy is allowed by non-determinism
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; in the spec, see https://webassembly.github.io/spec/core/bikeshed/index.html#nan-propagation%E2%91%A0.
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; run: %fmax_f64x2([-0x0.0 -0x1.0], [+0x0.0 0x1.0]) == [+0x0.0 0x1.0]
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; run: %fmax_f64x2([-NaN NaN], [0x0.0 0x100.0]) == [-NaN NaN]
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; run: %fmax_f64x2([NaN 0.0], [0.0 0.0]) == [NaN 0.0]
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; run: %fmax_f64x2([-NaN 0.0], [0x1.0 0.0]) == [-NaN 0.0]
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; run: %fmax_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [NaN 0.0]
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function %fmin_f64x2(f64x2, f64x2) -> f64x2 {
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block0(v0: f64x2, v1: f64x2):
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v2 = fmin v0, v1
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return v2
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}
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; note below how NaNs are quieted and negative: this is due to non-determinism in the spec for NaNs, see
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; https://webassembly.github.io/spec/core/bikeshed/index.html#nan-propagation%E2%91%A0.
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; run: %fmin_f64x2([-0x0.0 -0x1.0], [+0x0.0 0x1.0]) == [-0x0.0 -0x1.0]
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; run: %fmin_f64x2([-NaN 0x100.0], [0.0 NaN]) == [-NaN -NaN]
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; run: %fmin_f64x2([NaN 0.0], [0.0 0.0]) == [-NaN 0.0]
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; run: %fmin_f64x2([-NaN 0.0], [0x1.0 0.0]) == [-NaN 0.0]
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; run: %fmin_f64x2([NaN:0x42 0.0], [0x1.0 0.0]) == [-NaN 0.0]
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;function %fneg_f64x2() -> b1 {
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;block0:
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; v0 = vconst.f64x2 [0x1.0 -0x1.0]
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; v1 = fneg v0
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;
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; v2 = vconst.f64x2 [-0x1.0 0x1.0]
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; v3 = fcmp eq v1, v2
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; v4 = vall_true v3
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;
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; return v4
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;}
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; _run
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;function %fneg_f32x4() -> b1 {
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;block0:
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; v0 = vconst.f32x4 [0x0.0 -0x0.0 -Inf Inf]
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; v1 = fneg v0
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;
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; v2 = vconst.f32x4 [-0x0.0 0x0.0 Inf -Inf]
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; v3 = fcmp eq v1, v2
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; v4 = vall_true v3
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;
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; return v4
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;}
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; _run
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;function %fabs_f32x4() -> b1 {
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;block0:
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; v0 = vconst.f32x4 [0x0.0 -0x1.0 0x2.0 -0x3.0]
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; v1 = fabs v0
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;
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; v2 = vconst.f32x4 [0x0.0 0x1.0 0x2.0 0x3.0]
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; v3 = fcmp eq v1, v2
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; v4 = vall_true v3
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;
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; return v4
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;}
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; _run
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;function %average_rounding_i16x8() -> b1 {
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;block0:
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; v0 = vconst.i16x8 [0 0 0 1 42 19 -1 0xffff]
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; v1 = vconst.i16x8 [0 1 2 4 42 18 -1 0]
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; v2 = vconst.i16x8 [0 1 1 3 42 19 -1 0x8000]
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;
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; v3 = avg_round v0, v1
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; v4 = icmp eq v2, v3
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; v5 = vall_true v4
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;
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; return v5
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;}
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; _run
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function %iabs(i32x4) -> i32x4 {
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block0(v0: i32x4):
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v1 = iabs v0
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return v1
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}
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; run: %iabs([-42 -1 0 1]) == [42 1 0 1]
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