Jakob Stoklund Olesen 89a24b2f13 Rename ScalarType to LaneType. ...

The word "scalar" is a bit vague and tends to mean "non-vector". Since
we are about to add new CPU flag value types that can't appear as vector
lanes, make the distinction clear: LaneType represents value types that
can appear as a vector lane.

Also replace the Type::is_scalar() method with an is_vector() method.

2017-10-12 10:39:12 -07:00

..

.gitignore

Initial Sphinx configuration.

2016-01-12 16:51:35 -08:00

compare-llvm.rst

Documentation fixes (#103)

2017-06-22 12:01:32 -07:00

conf.py

Move the 'meta' dir to 'lib/cretonne/meta'.

2016-10-17 14:19:23 -07:00

cton_domain.py

Begin an Intel-specific instruction group.

2017-07-18 11:20:00 -07:00

cton_lexer.py

Add heap_addr custom legalization.

2017-08-24 14:44:47 -07:00

example.c

Update language reference.

2016-01-21 14:25:16 -08:00

example.cton

Add heaps to the Cretonne IL.

2017-08-23 14:15:59 -07:00

heapex-dyn.cton

Add heap_addr custom legalization.

2017-08-24 14:44:47 -07:00

heapex-sm32.cton

Add heap_addr custom legalization.

2017-08-24 14:44:47 -07:00

heapex-sm64.cton

Add heap_addr custom legalization.

2017-08-24 14:44:47 -07:00

index.rst

Start a design document for the Cretonne register allocator.

2016-11-21 17:00:16 -08:00

langref.rst

Add regspill and regfill instructions.

2017-10-04 17:02:09 -07:00

make.bat

Initial Sphinx configuration.

2016-01-12 16:51:35 -08:00

Makefile

Add global variables to Cretonne IL.

2017-08-17 14:41:27 -07:00

metaref.rst

Rename ScalarType to LaneType.

2017-10-12 10:39:12 -07:00

regalloc.rst

Documentation fixes (#103)

2017-06-22 12:01:32 -07:00

testing.rst

Documentation fixes (#103)

2017-06-22 12:01:32 -07:00