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83bb6fd4c81ad49d3217584337824e69702f909e
wasmtime/cranelift/codegen
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Ulrich Weigand 83bb6fd4c8 s390x: Fix regalloc checker error (#4973) 
For ShiftRR and VecShiftRR, if shift_reg is zero_reg(), the
instruction does not actually use any register value.

Fixes #4969
2022-09-28 08:25:23 -07:00
..
benches
Fix cranelift-codegen benches
2021-10-10 14:19:08 +02:00
meta
add riscv64 backend for cranelift. (#4271)
2022-09-27 17:30:31 -07:00
shared
Leverage Cargo's workspace inheritance feature (#4905)
2022-09-26 11:30:01 -05:00
src
s390x: Fix regalloc checker error (#4973)
2022-09-28 08:25:23 -07:00
build.rs
add riscv64 backend for cranelift. (#4271)
2022-09-27 17:30:31 -07:00
Cargo.toml
add riscv64 backend for cranelift. (#4271)
2022-09-27 17:30:31 -07:00
LICENSE
moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
2019-01-28 15:56:54 -08:00
README.md
moved crates in lib/ to src/, renamed crates, modified some files' text (#660)
2019-01-28 15:56:54 -08:00

README.md

This crate contains the core Cranelift code generator. It translates code from an intermediate representation into executable machine code.