b077854b57
Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
553 lines
11 KiB
Plaintext
553 lines
11 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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target aarch64
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function %stack_addr_small() -> i64 {
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ss0 = explicit_slot 8
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block0:
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v0 = stack_addr.i64 ss0
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return v0
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; sub sp, sp, #16
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; block0:
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; mov x0, sp
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; add sp, sp, #16
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; ldp fp, lr, [sp], #16
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; ret
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function %stack_addr_big() -> i64 {
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ss0 = explicit_slot 100000
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ss1 = explicit_slot 8
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block0:
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v0 = stack_addr.i64 ss0
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return v0
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; movz w16, #34480
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; movk w16, w16, #1, LSL #16
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; sub sp, sp, x16, UXTX
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; block0:
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; mov x0, sp
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; movz w16, #34480
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; movk w16, w16, #1, LSL #16
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; add sp, sp, x16, UXTX
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; ldp fp, lr, [sp], #16
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; ret
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function %stack_load_small() -> i64 {
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ss0 = explicit_slot 8
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block0:
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v0 = stack_load.i64 ss0
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return v0
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; sub sp, sp, #16
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; block0:
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; mov x1, sp
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; ldr x0, [x1]
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; add sp, sp, #16
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; ldp fp, lr, [sp], #16
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; ret
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function %stack_load_big() -> i64 {
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ss0 = explicit_slot 100000
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ss1 = explicit_slot 8
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block0:
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v0 = stack_load.i64 ss0
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return v0
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; movz w16, #34480
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; movk w16, w16, #1, LSL #16
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; sub sp, sp, x16, UXTX
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; block0:
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; mov x1, sp
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; ldr x0, [x1]
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; movz w16, #34480
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; movk w16, w16, #1, LSL #16
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; add sp, sp, x16, UXTX
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; ldp fp, lr, [sp], #16
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; ret
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function %stack_store_small(i64) {
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ss0 = explicit_slot 8
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block0(v0: i64):
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stack_store.i64 v0, ss0
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return
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; sub sp, sp, #16
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; block0:
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; mov x2, sp
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; str x0, [x2]
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; add sp, sp, #16
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; ldp fp, lr, [sp], #16
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; ret
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function %stack_store_big(i64) {
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ss0 = explicit_slot 100000
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ss1 = explicit_slot 8
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block0(v0: i64):
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stack_store.i64 v0, ss0
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return
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; movz w16, #34480
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; movk w16, w16, #1, LSL #16
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; sub sp, sp, x16, UXTX
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; block0:
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; mov x2, sp
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; str x0, [x2]
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; movz w16, #34480
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; movk w16, w16, #1, LSL #16
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; add sp, sp, x16, UXTX
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; ldp fp, lr, [sp], #16
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; ret
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function %i8_spill_slot(i8) -> i8, i64 {
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ss0 = explicit_slot 1000
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block0(v0: i8):
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v1 = iconst.i64 1
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v2 = iconst.i64 2
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v3 = iconst.i64 3
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v4 = iconst.i64 4
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v5 = iconst.i64 5
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v6 = iconst.i64 6
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v7 = iconst.i64 7
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v8 = iconst.i64 8
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v9 = iconst.i64 9
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v10 = iconst.i64 10
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v11 = iconst.i64 11
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v12 = iconst.i64 12
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v13 = iconst.i64 13
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v14 = iconst.i64 14
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v15 = iconst.i64 15
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v16 = iconst.i64 16
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v17 = iconst.i64 17
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v18 = iconst.i64 18
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v19 = iconst.i64 19
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v20 = iconst.i64 20
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v21 = iconst.i64 21
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v22 = iconst.i64 22
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v23 = iconst.i64 23
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v24 = iconst.i64 24
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v25 = iconst.i64 25
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v26 = iconst.i64 26
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v27 = iconst.i64 27
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v28 = iconst.i64 28
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v29 = iconst.i64 29
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v30 = iconst.i64 30
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v31 = iconst.i64 31
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v32 = iconst.i64 32
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v33 = iconst.i64 33
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v34 = iconst.i64 34
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v35 = iconst.i64 35
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v36 = iconst.i64 36
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v37 = iconst.i64 37
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v38 = iconst.i64 38
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v39 = iconst.i64 39
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v40 = iconst.i64 30
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v41 = iconst.i64 31
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v42 = iconst.i64 32
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v43 = iconst.i64 33
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v44 = iconst.i64 34
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v45 = iconst.i64 35
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v46 = iconst.i64 36
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v47 = iconst.i64 37
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v48 = iconst.i64 38
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v49 = iconst.i64 39
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v50 = iconst.i64 30
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v51 = iconst.i64 31
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v52 = iconst.i64 32
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v53 = iconst.i64 33
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v54 = iconst.i64 34
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v55 = iconst.i64 35
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v56 = iconst.i64 36
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v57 = iconst.i64 37
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v58 = iconst.i64 38
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v59 = iconst.i64 39
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v60 = iconst.i64 30
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v61 = iconst.i64 31
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v62 = iconst.i64 32
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v63 = iconst.i64 33
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v64 = iconst.i64 34
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v65 = iconst.i64 35
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v66 = iconst.i64 36
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v67 = iconst.i64 37
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v68 = iconst.i64 38
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v69 = iconst.i64 39
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v70 = iadd.i64 v1, v2
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v71 = iadd.i64 v3, v4
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v72 = iadd.i64 v5, v6
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v73 = iadd.i64 v7, v8
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v74 = iadd.i64 v9, v10
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v75 = iadd.i64 v11, v12
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v76 = iadd.i64 v13, v14
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v77 = iadd.i64 v15, v16
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v78 = iadd.i64 v17, v18
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v79 = iadd.i64 v19, v20
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v80 = iadd.i64 v21, v22
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v81 = iadd.i64 v23, v24
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v82 = iadd.i64 v25, v26
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v83 = iadd.i64 v27, v28
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v84 = iadd.i64 v29, v30
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v85 = iadd.i64 v31, v32
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v86 = iadd.i64 v33, v34
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v87 = iadd.i64 v35, v36
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v88 = iadd.i64 v37, v38
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v89 = iadd.i64 v39, v40
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v90 = iadd.i64 v41, v42
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v91 = iadd.i64 v43, v44
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v92 = iadd.i64 v45, v46
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v93 = iadd.i64 v47, v48
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v94 = iadd.i64 v49, v50
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v95 = iadd.i64 v51, v52
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v96 = iadd.i64 v53, v54
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v97 = iadd.i64 v55, v56
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v98 = iadd.i64 v57, v58
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v99 = iadd.i64 v59, v60
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v100 = iadd.i64 v61, v62
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v101 = iadd.i64 v63, v64
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v102 = iadd.i64 v65, v66
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v103 = iadd.i64 v67, v68
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v104 = iadd.i64 v69, v70
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v105 = iadd.i64 v71, v72
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v106 = iadd.i64 v73, v74
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v107 = iadd.i64 v75, v76
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v108 = iadd.i64 v77, v78
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v109 = iadd.i64 v79, v80
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v110 = iadd.i64 v81, v82
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v111 = iadd.i64 v83, v84
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v112 = iadd.i64 v85, v86
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v113 = iadd.i64 v87, v88
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v114 = iadd.i64 v89, v90
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v115 = iadd.i64 v91, v92
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v116 = iadd.i64 v93, v94
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v117 = iadd.i64 v95, v96
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v118 = iadd.i64 v97, v98
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v119 = iadd.i64 v99, v100
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v120 = iadd.i64 v101, v102
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v121 = iadd.i64 v103, v104
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v122 = iadd.i64 v105, v106
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v123 = iadd.i64 v107, v108
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v124 = iadd.i64 v109, v110
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v125 = iadd.i64 v111, v112
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v126 = iadd.i64 v113, v114
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v127 = iadd.i64 v115, v116
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v128 = iadd.i64 v117, v118
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v129 = iadd.i64 v119, v120
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v130 = iadd.i64 v121, v122
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v131 = iadd.i64 v123, v124
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v132 = iadd.i64 v125, v126
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v133 = iadd.i64 v127, v128
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v134 = iadd.i64 v129, v130
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v135 = iadd.i64 v131, v132
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v136 = iadd.i64 v133, v134
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v137 = iadd.i64 v135, v136
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return v0, v137
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; stp x27, x28, [sp, #-16]!
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; stp x25, x26, [sp, #-16]!
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; stp x23, x24, [sp, #-16]!
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; stp x21, x22, [sp, #-16]!
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; stp x19, x20, [sp, #-16]!
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; sub sp, sp, #1152
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; block0:
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; str x0, [sp, #1000]
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; movz x6, #2
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; add x9, x6, #1
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; str x9, [sp, #1136]
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; movz x6, #4
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; add x10, x6, #3
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; str x10, [sp, #1128]
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; movz x6, #6
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; add x11, x6, #5
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; str x11, [sp, #1120]
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; movz x6, #8
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; add x12, x6, #7
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; str x12, [sp, #1112]
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; movz x6, #10
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; add x13, x6, #9
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; str x13, [sp, #1104]
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; movz x6, #12
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; add x14, x6, #11
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; str x14, [sp, #1096]
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; movz x6, #14
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; add x15, x6, #13
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; str x15, [sp, #1088]
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; movz x6, #16
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; add x1, x6, #15
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; str x1, [sp, #1080]
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; movz x6, #18
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; add x2, x6, #17
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; str x2, [sp, #1072]
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; movz x6, #20
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; add x3, x6, #19
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; str x3, [sp, #1064]
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; movz x6, #22
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; add x4, x6, #21
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; str x4, [sp, #1056]
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; movz x6, #24
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; add x5, x6, #23
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; str x5, [sp, #1048]
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; movz x6, #26
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; add x6, x6, #25
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; str x6, [sp, #1040]
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; movz x6, #28
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; add x7, x6, #27
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; str x7, [sp, #1032]
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; movz x6, #30
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; add x24, x6, #29
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; str x24, [sp, #1024]
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; movz x6, #32
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; add x25, x6, #31
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; str x25, [sp, #1016]
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; movz x6, #34
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; add x26, x6, #33
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; movz x6, #36
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; add x27, x6, #35
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; str x27, [sp, #1008]
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; movz x6, #38
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; add x27, x6, #37
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; movz x6, #30
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; add x28, x6, #39
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; movz x6, #32
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; add x21, x6, #31
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; movz x6, #34
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; add x19, x6, #33
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; movz x6, #36
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; add x20, x6, #35
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; movz x6, #38
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; add x22, x6, #37
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; movz x6, #30
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; add x23, x6, #39
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; movz x6, #32
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; add x0, x6, #31
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; movz x6, #34
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; add x8, x6, #33
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; movz x6, #36
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; add x9, x6, #35
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; movz x6, #38
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; add x10, x6, #37
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; movz x6, #30
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; add x11, x6, #39
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; movz x6, #32
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; add x12, x6, #31
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; movz x6, #34
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; add x13, x6, #33
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; movz x6, #36
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; add x14, x6, #35
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; movz x6, #38
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; add x15, x6, #37
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; ldr x1, [sp, #1136]
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; add x1, x1, #39
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; ldr x3, [sp, #1120]
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; ldr x2, [sp, #1128]
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; add x2, x2, x3
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; ldr x3, [sp, #1104]
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; ldr x6, [sp, #1112]
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; add x3, x6, x3
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; ldr x4, [sp, #1088]
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; ldr x5, [sp, #1096]
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; add x4, x5, x4
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; ldr x5, [sp, #1072]
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; ldr x6, [sp, #1080]
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; add x5, x6, x5
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; ldr x7, [sp, #1056]
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; ldr x6, [sp, #1064]
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; add x6, x6, x7
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; ldr x7, [sp, #1040]
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; ldr x24, [sp, #1048]
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; add x7, x24, x7
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; ldr x24, [sp, #1024]
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; ldr x25, [sp, #1032]
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; add x24, x25, x24
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; ldr x25, [sp, #1016]
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; add x25, x25, x26
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; ldr x26, [sp, #1008]
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; add x26, x26, x27
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; add x27, x28, x21
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; add x28, x19, x20
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; add x23, x22, x23
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; add x8, x0, x8
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; add x9, x9, x10
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; add x10, x11, x12
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; add x11, x13, x14
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; add x12, x15, x1
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; add x13, x2, x3
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; add x14, x4, x5
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; add x7, x6, x7
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; add x15, x24, x25
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; add x0, x26, x27
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; add x1, x28, x23
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; add x8, x8, x9
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; add x9, x10, x11
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; add x10, x12, x13
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; add x7, x14, x7
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; add x11, x15, x0
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; add x8, x1, x8
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; add x9, x9, x10
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; add x7, x7, x11
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; add x8, x8, x9
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; add x1, x7, x8
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; ldr x0, [sp, #1000]
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; add sp, sp, #1152
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; ldp x19, x20, [sp], #16
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; ldp x21, x22, [sp], #16
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; ldp x23, x24, [sp], #16
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; ldp x25, x26, [sp], #16
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; ldp x27, x28, [sp], #16
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; ldp fp, lr, [sp], #16
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; ret
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function %i128_stack_store(i128) {
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ss0 = explicit_slot 16
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block0(v0: i128):
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stack_store.i128 v0, ss0
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return
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; sub sp, sp, #16
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; block0:
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; mov x4, sp
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; stp x0, x1, [x4]
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; add sp, sp, #16
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; ldp fp, lr, [sp], #16
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; ret
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function %i128_stack_store_inst_offset(i128) {
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ss0 = explicit_slot 16
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ss1 = explicit_slot 16
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block0(v0: i128):
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stack_store.i128 v0, ss1+16
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return
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; sub sp, sp, #32
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; block0:
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; add x4, sp, #32
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; stp x0, x1, [x4]
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; add sp, sp, #32
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; ldp fp, lr, [sp], #16
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; ret
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function %i128_stack_store_big(i128) {
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ss0 = explicit_slot 100000
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ss1 = explicit_slot 8
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block0(v0: i128):
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stack_store.i128 v0, ss0
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return
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}
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; stp fp, lr, [sp, #-16]!
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; mov fp, sp
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; movz w16, #34480
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|
; movk w16, w16, #1, LSL #16
|
|
; sub sp, sp, x16, UXTX
|
|
; block0:
|
|
; mov x4, sp
|
|
; stp x0, x1, [x4]
|
|
; movz w16, #34480
|
|
; movk w16, w16, #1, LSL #16
|
|
; add sp, sp, x16, UXTX
|
|
; ldp fp, lr, [sp], #16
|
|
; ret
|
|
|
|
function %i128_stack_load() -> i128 {
|
|
ss0 = explicit_slot 16
|
|
|
|
block0:
|
|
v0 = stack_load.i128 ss0
|
|
return v0
|
|
}
|
|
|
|
; stp fp, lr, [sp, #-16]!
|
|
; mov fp, sp
|
|
; sub sp, sp, #16
|
|
; block0:
|
|
; mov x3, sp
|
|
; ldp x0, x1, [x3]
|
|
; add sp, sp, #16
|
|
; ldp fp, lr, [sp], #16
|
|
; ret
|
|
|
|
function %i128_stack_load_inst_offset() -> i128 {
|
|
ss0 = explicit_slot 16
|
|
ss1 = explicit_slot 16
|
|
|
|
block0:
|
|
v0 = stack_load.i128 ss1+16
|
|
return v0
|
|
}
|
|
|
|
; stp fp, lr, [sp, #-16]!
|
|
; mov fp, sp
|
|
; sub sp, sp, #32
|
|
; block0:
|
|
; add x3, sp, #32
|
|
; ldp x0, x1, [x3]
|
|
; add sp, sp, #32
|
|
; ldp fp, lr, [sp], #16
|
|
; ret
|
|
|
|
function %i128_stack_load_big() -> i128 {
|
|
ss0 = explicit_slot 100000
|
|
ss1 = explicit_slot 8
|
|
|
|
block0:
|
|
v0 = stack_load.i128 ss0
|
|
return v0
|
|
}
|
|
|
|
; stp fp, lr, [sp, #-16]!
|
|
; mov fp, sp
|
|
; movz w16, #34480
|
|
; movk w16, w16, #1, LSL #16
|
|
; sub sp, sp, x16, UXTX
|
|
; block0:
|
|
; mov x3, sp
|
|
; ldp x0, x1, [x3]
|
|
; movz w16, #34480
|
|
; movk w16, w16, #1, LSL #16
|
|
; add sp, sp, x16, UXTX
|
|
; ldp fp, lr, [sp], #16
|
|
; ret
|
|
|