b077854b57
Modify return pseudo-instructions to have pairs of registers: virtual and real. This allows us to constrain the virtual registers to the real ones specified by the abi, instead of directly emitting moves to those real registers.
112 lines
1.9 KiB
Plaintext
112 lines
1.9 KiB
Plaintext
test compile precise-output
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target aarch64
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function %swidenhigh_i8x16(i8) -> i16x8 {
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gv0 = dyn_scale_target_const.i16x8
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gv1 = dyn_scale_target_const.i8x16
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dt0 = i8x16*gv1
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dt1 = i16x8*gv0
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block0(v0: i8):
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v1 = splat.dt0 v0
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v2 = swiden_high v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v4.16b, w0
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; sxtl2 v0.8h, v4.16b
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; ret
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function %swidenhigh_i16x8(i16) -> i32x4 {
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gv0 = dyn_scale_target_const.i32x4
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gv1 = dyn_scale_target_const.i16x8
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dt0 = i16x8*gv1
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dt1 = i32x4*gv0
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block0(v0: i16):
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v1 = splat.dt0 v0
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v2 = swiden_high v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v4.8h, w0
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; sxtl2 v0.4s, v4.8h
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; ret
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function %swidenhigh_i32x4(i32) -> i64x2 {
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gv0 = dyn_scale_target_const.i32x4
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gv1 = dyn_scale_target_const.i64x2
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dt0 = i64x2*gv1
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dt1 = i32x4*gv0
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block0(v0: i32):
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v1 = splat.dt1 v0
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v2 = swiden_high v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v4.4s, w0
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; sxtl2 v0.2d, v4.4s
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; ret
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function %swidenlow_i8x16(i8) -> i16x8 {
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gv0 = dyn_scale_target_const.i16x8
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gv1 = dyn_scale_target_const.i8x16
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dt0 = i8x16*gv1
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dt1 = i16x8*gv0
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block0(v0: i8):
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v1 = splat.dt0 v0
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v2 = swiden_low v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v4.16b, w0
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; sxtl v0.8h, v4.8b
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; ret
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function %swidenlow_i16x8(i16) -> i32x4 {
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gv0 = dyn_scale_target_const.i32x4
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gv1 = dyn_scale_target_const.i16x8
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dt0 = i16x8*gv1
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dt1 = i32x4*gv0
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block0(v0: i16):
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v1 = splat.dt0 v0
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v2 = swiden_low v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v4.8h, w0
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; sxtl v0.4s, v4.4h
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; ret
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function %swidenlow_i32x4(i32) -> i64x2 {
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gv0 = dyn_scale_target_const.i32x4
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gv1 = dyn_scale_target_const.i64x2
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dt0 = i64x2*gv1
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dt1 = i32x4*gv0
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block0(v0: i32):
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v1 = splat.dt1 v0
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v2 = swiden_low v1
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v3 = extract_vector v2, 0
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return v3
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}
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; block0:
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; dup v4.4s, w0
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; sxtl v0.2d, v4.2s
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; ret
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