7f3b807597
A CallConv enum on every function signature makes it possible to
generate calls to functions with different calling conventions within
the same ISA / within a single function.
The calling conventions also serve as a way of customizing Cretonne's
behavior when embedded inside a VM. As an example, the SpiderWASM
calling convention is used to compile WebAssembly functions that run
inside the SpiderMonkey virtual machine.
All function signatures must have a calling convention at the end, so
this changes the textual IL syntax.
Before:
sig1 = signature(i32, f64) -> f64
After
sig1 = (i32, f64) -> f64 native
sig2 = (i32) spiderwasm
When printing functions, the signature goes after the return types:
function %r1() -> i32, f32 spiderwasm {
ebb1:
...
}
In the parser, this calling convention is optional and defaults to
"native". This is mostly to avoid updating all the existing test cases
under filetests/. When printing a function, the calling convention is
always included, including for "native" functions.
369 lines
14 KiB
Plaintext
369 lines
14 KiB
Plaintext
; binary emission of 32-bit code.
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test binemit
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isa intel haswell
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; The binary encodings can be verified with the command:
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;
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; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary32.cton | llvm-mc -show-encoding -triple=i386
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;
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function %I32() {
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fn0 = function %foo()
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sig0 = ()
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ebb0:
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; asm: movl $1, %ecx
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[-,%rcx] v1 = iconst.i32 1 ; bin: b9 00000001
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; asm: movl $2, %esi
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[-,%rsi] v2 = iconst.i32 2 ; bin: be 00000002
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; Integer Register-Register Operations.
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; asm: addl %esi, %ecx
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[-,%rcx] v10 = iadd v1, v2 ; bin: 01 f1
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; asm: addl %ecx, %esi
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[-,%rsi] v11 = iadd v2, v1 ; bin: 01 ce
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; asm: subl %esi, %ecx
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[-,%rcx] v12 = isub v1, v2 ; bin: 29 f1
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; asm: subl %ecx, %esi
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[-,%rsi] v13 = isub v2, v1 ; bin: 29 ce
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; asm: andl %esi, %ecx
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[-,%rcx] v14 = band v1, v2 ; bin: 21 f1
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; asm: andl %ecx, %esi
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[-,%rsi] v15 = band v2, v1 ; bin: 21 ce
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; asm: orl %esi, %ecx
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[-,%rcx] v16 = bor v1, v2 ; bin: 09 f1
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; asm: orl %ecx, %esi
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[-,%rsi] v17 = bor v2, v1 ; bin: 09 ce
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; asm: xorl %esi, %ecx
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[-,%rcx] v18 = bxor v1, v2 ; bin: 31 f1
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; asm: xorl %ecx, %esi
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[-,%rsi] v19 = bxor v2, v1 ; bin: 31 ce
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; Dynamic shifts take the shift amount in %rcx.
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; asm: shll %cl, %esi
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[-,%rsi] v20 = ishl v2, v1 ; bin: d3 e6
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; asm: shll %cl, %ecx
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[-,%rcx] v21 = ishl v1, v1 ; bin: d3 e1
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; asm: shrl %cl, %esi
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[-,%rsi] v22 = ushr v2, v1 ; bin: d3 ee
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; asm: shrl %cl, %ecx
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[-,%rcx] v23 = ushr v1, v1 ; bin: d3 e9
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; asm: sarl %cl, %esi
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[-,%rsi] v24 = sshr v2, v1 ; bin: d3 fe
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; asm: sarl %cl, %ecx
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[-,%rcx] v25 = sshr v1, v1 ; bin: d3 f9
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; asm: roll %cl, %esi
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[-,%rsi] v26 = rotl v2, v1 ; bin: d3 c6
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; asm: roll %cl, %ecx
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[-,%rcx] v27 = rotl v1, v1 ; bin: d3 c1
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; asm: rorl %cl, %esi
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[-,%rsi] v28 = rotr v2, v1 ; bin: d3 ce
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; asm: rorl %cl, %ecx
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[-,%rcx] v29 = rotr v1, v1 ; bin: d3 c9
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; Integer Register - Immediate 8-bit operations.
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; The 8-bit immediate is sign-extended.
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; asm: addl $-128, %ecx
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[-,%rcx] v30 = iadd_imm v1, -128 ; bin: 83 c1 80
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; asm: addl $10, %esi
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[-,%rsi] v31 = iadd_imm v2, 10 ; bin: 83 c6 0a
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; asm: andl $-128, %ecx
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[-,%rcx] v32 = band_imm v1, -128 ; bin: 83 e1 80
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; asm: andl $10, %esi
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[-,%rsi] v33 = band_imm v2, 10 ; bin: 83 e6 0a
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; asm: orl $-128, %ecx
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[-,%rcx] v34 = bor_imm v1, -128 ; bin: 83 c9 80
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; asm: orl $10, %esi
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[-,%rsi] v35 = bor_imm v2, 10 ; bin: 83 ce 0a
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; asm: xorl $-128, %ecx
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[-,%rcx] v36 = bxor_imm v1, -128 ; bin: 83 f1 80
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; asm: xorl $10, %esi
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[-,%rsi] v37 = bxor_imm v2, 10 ; bin: 83 f6 0a
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; Integer Register - Immediate 32-bit operations.
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; asm: addl $-128000, %ecx
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[-,%rcx] v40 = iadd_imm v1, -128000 ; bin: 81 c1 fffe0c00
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; asm: addl $1000000, %esi
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[-,%rsi] v41 = iadd_imm v2, 1000000 ; bin: 81 c6 000f4240
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; asm: andl $-128000, %ecx
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[-,%rcx] v42 = band_imm v1, -128000 ; bin: 81 e1 fffe0c00
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; asm: andl $1000000, %esi
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[-,%rsi] v43 = band_imm v2, 1000000 ; bin: 81 e6 000f4240
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; asm: orl $-128000, %ecx
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[-,%rcx] v44 = bor_imm v1, -128000 ; bin: 81 c9 fffe0c00
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; asm: orl $1000000, %esi
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[-,%rsi] v45 = bor_imm v2, 1000000 ; bin: 81 ce 000f4240
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; asm: xorl $-128000, %ecx
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[-,%rcx] v46 = bxor_imm v1, -128000 ; bin: 81 f1 fffe0c00
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; asm: xorl $1000000, %esi
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[-,%rsi] v47 = bxor_imm v2, 1000000 ; bin: 81 f6 000f4240
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; More arithmetic.
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; asm: imull %esi, %ecx
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[-,%rcx] v50 = imul v1, v2 ; bin: 0f af ce
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; asm: imull %ecx, %esi
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[-,%rsi] v51 = imul v2, v1 ; bin: 0f af f1
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; asm: movl $1, %eax
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[-,%rax] v52 = iconst.i32 1 ; bin: b8 00000001
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; asm: movl $2, %edx
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[-,%rdx] v53 = iconst.i32 2 ; bin: ba 00000002
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; asm: idivl %ecx
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[-,%rax,%rdx] v54, v55 = x86_sdivmodx v52, v53, v1 ; bin: f7 f9
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; asm: idivl %esi
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[-,%rax,%rdx] v56, v57 = x86_sdivmodx v52, v53, v2 ; bin: f7 fe
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; asm: divl %ecx
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[-,%rax,%rdx] v58, v59 = x86_udivmodx v52, v53, v1 ; bin: f7 f1
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; asm: divl %esi
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[-,%rax,%rdx] v60, v61 = x86_udivmodx v52, v53, v2 ; bin: f7 f6
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; Register copies.
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; asm: movl %esi, %ecx
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[-,%rcx] v80 = copy v2 ; bin: 89 f1
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; asm: movl %ecx, %esi
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[-,%rsi] v81 = copy v1 ; bin: 89 ce
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; Load/Store instructions.
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; Register indirect addressing with no displacement.
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; asm: movl %ecx, (%esi)
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store v1, v2 ; bin: 89 0e
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; asm: movl %esi, (%ecx)
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store v2, v1 ; bin: 89 31
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; asm: movw %cx, (%esi)
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istore16 v1, v2 ; bin: 66 89 0e
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; asm: movw %si, (%ecx)
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istore16 v2, v1 ; bin: 66 89 31
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; asm: movb %cl, (%esi)
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istore8 v1, v2 ; bin: 88 0e
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; Can't store %sil in 32-bit mode (needs REX prefix).
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; asm: movl (%ecx), %edi
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[-,%rdi] v100 = load.i32 v1 ; bin: 8b 39
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; asm: movl (%esi), %edx
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[-,%rdx] v101 = load.i32 v2 ; bin: 8b 16
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; asm: movzwl (%ecx), %edi
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[-,%rdi] v102 = uload16.i32 v1 ; bin: 0f b7 39
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; asm: movzwl (%esi), %edx
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[-,%rdx] v103 = uload16.i32 v2 ; bin: 0f b7 16
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; asm: movswl (%ecx), %edi
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[-,%rdi] v104 = sload16.i32 v1 ; bin: 0f bf 39
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; asm: movswl (%esi), %edx
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[-,%rdx] v105 = sload16.i32 v2 ; bin: 0f bf 16
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; asm: movzbl (%ecx), %edi
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[-,%rdi] v106 = uload8.i32 v1 ; bin: 0f b6 39
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; asm: movzbl (%esi), %edx
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[-,%rdx] v107 = uload8.i32 v2 ; bin: 0f b6 16
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; asm: movsbl (%ecx), %edi
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[-,%rdi] v108 = sload8.i32 v1 ; bin: 0f be 39
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; asm: movsbl (%esi), %edx
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[-,%rdx] v109 = sload8.i32 v2 ; bin: 0f be 16
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; Register-indirect with 8-bit signed displacement.
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; asm: movl %ecx, 100(%esi)
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store v1, v2+100 ; bin: 89 4e 64
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; asm: movl %esi, -100(%ecx)
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store v2, v1-100 ; bin: 89 71 9c
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; asm: movw %cx, 100(%esi)
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istore16 v1, v2+100 ; bin: 66 89 4e 64
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; asm: movw %si, -100(%ecx)
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istore16 v2, v1-100 ; bin: 66 89 71 9c
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; asm: movb %cl, 100(%esi)
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istore8 v1, v2+100 ; bin: 88 4e 64
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; asm: movl 50(%ecx), %edi
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[-,%rdi] v110 = load.i32 v1+50 ; bin: 8b 79 32
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; asm: movl -50(%esi), %edx
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[-,%rdx] v111 = load.i32 v2-50 ; bin: 8b 56 ce
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; asm: movzwl 50(%ecx), %edi
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[-,%rdi] v112 = uload16.i32 v1+50 ; bin: 0f b7 79 32
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; asm: movzwl -50(%esi), %edx
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[-,%rdx] v113 = uload16.i32 v2-50 ; bin: 0f b7 56 ce
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; asm: movswl 50(%ecx), %edi
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[-,%rdi] v114 = sload16.i32 v1+50 ; bin: 0f bf 79 32
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; asm: movswl -50(%esi), %edx
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[-,%rdx] v115 = sload16.i32 v2-50 ; bin: 0f bf 56 ce
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; asm: movzbl 50(%ecx), %edi
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[-,%rdi] v116 = uload8.i32 v1+50 ; bin: 0f b6 79 32
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; asm: movzbl -50(%esi), %edx
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[-,%rdx] v117 = uload8.i32 v2-50 ; bin: 0f b6 56 ce
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; asm: movsbl 50(%ecx), %edi
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[-,%rdi] v118 = sload8.i32 v1+50 ; bin: 0f be 79 32
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; asm: movsbl -50(%esi), %edx
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[-,%rdx] v119 = sload8.i32 v2-50 ; bin: 0f be 56 ce
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; Register-indirect with 32-bit signed displacement.
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; asm: movl %ecx, 10000(%esi)
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store v1, v2+10000 ; bin: 89 8e 00002710
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; asm: movl %esi, -10000(%ecx)
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store v2, v1-10000 ; bin: 89 b1 ffffd8f0
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; asm: movw %cx, 10000(%esi)
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istore16 v1, v2+10000 ; bin: 66 89 8e 00002710
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; asm: movw %si, -10000(%ecx)
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istore16 v2, v1-10000 ; bin: 66 89 b1 ffffd8f0
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; asm: movb %cl, 10000(%esi)
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istore8 v1, v2+10000 ; bin: 88 8e 00002710
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; asm: movl 50000(%ecx), %edi
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[-,%rdi] v120 = load.i32 v1+50000 ; bin: 8b b9 0000c350
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; asm: movl -50000(%esi), %edx
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[-,%rdx] v121 = load.i32 v2-50000 ; bin: 8b 96 ffff3cb0
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; asm: movzwl 50000(%ecx), %edi
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[-,%rdi] v122 = uload16.i32 v1+50000 ; bin: 0f b7 b9 0000c350
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; asm: movzwl -50000(%esi), %edx
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[-,%rdx] v123 = uload16.i32 v2-50000 ; bin: 0f b7 96 ffff3cb0
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; asm: movswl 50000(%ecx), %edi
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[-,%rdi] v124 = sload16.i32 v1+50000 ; bin: 0f bf b9 0000c350
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; asm: movswl -50000(%esi), %edx
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[-,%rdx] v125 = sload16.i32 v2-50000 ; bin: 0f bf 96 ffff3cb0
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; asm: movzbl 50000(%ecx), %edi
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[-,%rdi] v126 = uload8.i32 v1+50000 ; bin: 0f b6 b9 0000c350
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; asm: movzbl -50000(%esi), %edx
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[-,%rdx] v127 = uload8.i32 v2-50000 ; bin: 0f b6 96 ffff3cb0
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; asm: movsbl 50000(%ecx), %edi
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[-,%rdi] v128 = sload8.i32 v1+50000 ; bin: 0f be b9 0000c350
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; asm: movsbl -50000(%esi), %edx
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[-,%rdx] v129 = sload8.i32 v2-50000 ; bin: 0f be 96 ffff3cb0
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; Bit-counting instructions.
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; asm: popcntl %esi, %ecx
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[-,%rcx] v200 = popcnt v2 ; bin: f3 0f b8 ce
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; asm: popcntl %ecx, %esi
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[-,%rsi] v201 = popcnt v1 ; bin: f3 0f b8 f1
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; asm: lzcntl %esi, %ecx
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[-,%rcx] v202 = clz v2 ; bin: f3 0f bd ce
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; asm: lzcntl %ecx, %esi
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[-,%rsi] v203 = clz v1 ; bin: f3 0f bd f1
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; asm: tzcntl %esi, %ecx
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[-,%rcx] v204 = ctz v2 ; bin: f3 0f bc ce
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; asm: tzcntl %ecx, %esi
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[-,%rsi] v205 = ctz v1 ; bin: f3 0f bc f1
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; Integer comparisons.
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; asm: cmpl %esi, %ecx
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; asm: sete %bl
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[-,%rbx] v300 = icmp eq v1, v2 ; bin: 39 f1 0f 94 c3
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; asm: cmpl %ecx, %esi
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; asm: sete %dl
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[-,%rdx] v301 = icmp eq v2, v1 ; bin: 39 ce 0f 94 c2
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; asm: cmpl %esi, %ecx
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; asm: setne %bl
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[-,%rbx] v302 = icmp ne v1, v2 ; bin: 39 f1 0f 95 c3
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; asm: cmpl %ecx, %esi
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; asm: setne %dl
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[-,%rdx] v303 = icmp ne v2, v1 ; bin: 39 ce 0f 95 c2
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; asm: cmpl %esi, %ecx
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; asm: setl %bl
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[-,%rbx] v304 = icmp slt v1, v2 ; bin: 39 f1 0f 9c c3
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; asm: cmpl %ecx, %esi
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; asm: setl %dl
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[-,%rdx] v305 = icmp slt v2, v1 ; bin: 39 ce 0f 9c c2
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; asm: cmpl %esi, %ecx
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; asm: setge %bl
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[-,%rbx] v306 = icmp sge v1, v2 ; bin: 39 f1 0f 9d c3
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; asm: cmpl %ecx, %esi
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; asm: setge %dl
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[-,%rdx] v307 = icmp sge v2, v1 ; bin: 39 ce 0f 9d c2
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; asm: cmpl %esi, %ecx
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; asm: setg %bl
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[-,%rbx] v308 = icmp sgt v1, v2 ; bin: 39 f1 0f 9f c3
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; asm: cmpl %ecx, %esi
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; asm: setg %dl
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[-,%rdx] v309 = icmp sgt v2, v1 ; bin: 39 ce 0f 9f c2
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; asm: cmpl %esi, %ecx
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; asm: setle %bl
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[-,%rbx] v310 = icmp sle v1, v2 ; bin: 39 f1 0f 9e c3
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; asm: cmpl %ecx, %esi
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; asm: setle %dl
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[-,%rdx] v311 = icmp sle v2, v1 ; bin: 39 ce 0f 9e c2
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; asm: cmpl %esi, %ecx
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; asm: setb %bl
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[-,%rbx] v312 = icmp ult v1, v2 ; bin: 39 f1 0f 92 c3
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; asm: cmpl %ecx, %esi
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; asm: setb %dl
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[-,%rdx] v313 = icmp ult v2, v1 ; bin: 39 ce 0f 92 c2
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; asm: cmpl %esi, %ecx
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; asm: setae %bl
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[-,%rbx] v314 = icmp uge v1, v2 ; bin: 39 f1 0f 93 c3
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; asm: cmpl %ecx, %esi
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; asm: setae %dl
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[-,%rdx] v315 = icmp uge v2, v1 ; bin: 39 ce 0f 93 c2
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; asm: cmpl %esi, %ecx
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; asm: seta %bl
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[-,%rbx] v316 = icmp ugt v1, v2 ; bin: 39 f1 0f 97 c3
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; asm: cmpl %ecx, %esi
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; asm: seta %dl
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[-,%rdx] v317 = icmp ugt v2, v1 ; bin: 39 ce 0f 97 c2
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; asm: cmpl %esi, %ecx
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; asm: setbe %bl
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[-,%rbx] v318 = icmp ule v1, v2 ; bin: 39 f1 0f 96 c3
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; asm: cmpl %ecx, %esi
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; asm: setbe %dl
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[-,%rdx] v319 = icmp ule v2, v1 ; bin: 39 ce 0f 96 c2
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; Bool-to-int conversions.
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; asm: movzbl %bl, %ecx
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[-,%rcx] v350 = bint.i32 v300 ; bin: 0f b6 cb
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; asm: movzbl %dl, %esi
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[-,%rsi] v351 = bint.i32 v301 ; bin: 0f b6 f2
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; asm: call foo
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call fn0() ; bin: e8 PCRel4(fn0) 00000000
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; asm: call *%ecx
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call_indirect sig0, v1() ; bin: ff d1
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; asm: call *%esi
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call_indirect sig0, v2() ; bin: ff d6
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; asm: testl %ecx, %ecx
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; asm: je ebb1
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brz v1, ebb1 ; bin: 85 c9 74 0e
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; asm: testl %esi, %esi
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; asm: je ebb1
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brz v2, ebb1 ; bin: 85 f6 74 0a
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; asm: testl %ecx, %ecx
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; asm: jne ebb1
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brnz v1, ebb1 ; bin: 85 c9 75 06
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; asm: testl %esi, %esi
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; asm: jne ebb1
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brnz v2, ebb1 ; bin: 85 f6 75 02
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|
|
; asm: jmp ebb2
|
|
jump ebb2 ; bin: eb 01
|
|
|
|
; asm: ebb1:
|
|
ebb1:
|
|
; asm: ret
|
|
return ; bin: c3
|
|
|
|
; asm: ebb2:
|
|
ebb2:
|
|
trap ; bin: 0f 0b
|
|
}
|