48cf2c2f50
- Undo temporary changes to default features (`all-arch`) and a
signal-handler test.
- Remove `SIGTRAP` handler: no longer needed now that we've found an
"undefined opcode" option on ARM64.
- Rename pp.rs to pretty_print.rs in machinst/.
- Only use empty stack-probe on non-x86. As per a comment in
rust-lang/compiler-builtins [1], LLVM only supports stack probes on
x86 and x86-64. Thus, on any other CPU architecture, we cannot refer
to `__rust_probestack`, because it does not exist.
- Rename arm64 to aarch64.
- Use `target` directive in vcode filetests.
- Run the flags verifier, but without encinfo, when using new backends.
- Clean up warning overrides.
- Fix up use of casts: use u32::from(x) and siblings when possible,
u32::try_from(x).unwrap() when not, to avoid silent truncation.
- Take immutable `Function` borrows as input; we don't actually
mutate the input IR.
- Lots of other miscellaneous cleanups.
[1] cae3e6ea23/src/probestack.rs (L39)
244 lines
4.5 KiB
Plaintext
244 lines
4.5 KiB
Plaintext
test vcode
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target aarch64
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = iadd.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: add x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = isub.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sub x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = imul.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: madd x0, x0, x1, xzr
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = umulhi.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: umulh x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = smulhi.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: smulh x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = sdiv.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sdiv x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 2
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v2 = sdiv.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x1, #2
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; nextln: sdiv x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = udiv.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: udiv x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 2
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v2 = udiv.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: movz x1, #2
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; nextln: udiv x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = srem.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sdiv x2, x0, x1
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; nextln: msub x0, x2, x1, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = urem.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: udiv x2, x0, x1
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; nextln: msub x0, x2, x1, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = band.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: and x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bor.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: orr x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bxor.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: eor x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = band_not.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: bic x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bor_not.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: orn x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bxor_not.i64 v0, v1
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: eon x0, x0, x1
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = bnot.i64 v0
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: orn x0, xzr, x0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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