7b98be1bee
* Cranelift AArch64: Simplify leaf functions that do not use the stack Leaf functions that do not use the stack (e.g. do not clobber any callee-saved registers) do not need a frame record. Copyright (c) 2021, Arm Limited.
651 lines
11 KiB
Plaintext
651 lines
11 KiB
Plaintext
test compile
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set unwind_info=false
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target aarch64
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function %f1(f32, f32) -> f32 {
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block0(v0: f32, v1: f32):
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v2 = fadd v0, v1
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return v2
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}
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; check: fadd s0, s0, s1
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; nextln: ret
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function %f2(f64, f64) -> f64 {
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block0(v0: f64, v1: f64):
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v2 = fadd v0, v1
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return v2
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}
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; check: fadd d0, d0, d1
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; nextln: ret
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function %f3(f32, f32) -> f32 {
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block0(v0: f32, v1: f32):
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v2 = fsub v0, v1
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return v2
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}
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; check: fsub s0, s0, s1
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; nextln: ret
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function %f4(f64, f64) -> f64 {
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block0(v0: f64, v1: f64):
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v2 = fsub v0, v1
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return v2
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}
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; check: fsub d0, d0, d1
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; nextln: ret
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function %f5(f32, f32) -> f32 {
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block0(v0: f32, v1: f32):
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v2 = fmul v0, v1
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return v2
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}
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; check: fmul s0, s0, s1
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; nextln: ret
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function %f6(f64, f64) -> f64 {
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block0(v0: f64, v1: f64):
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v2 = fmul v0, v1
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return v2
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}
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; check: fmul d0, d0, d1
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; nextln: ret
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function %f7(f32, f32) -> f32 {
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block0(v0: f32, v1: f32):
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v2 = fdiv v0, v1
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return v2
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}
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; check: fdiv s0, s0, s1
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; nextln: ret
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function %f8(f64, f64) -> f64 {
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block0(v0: f64, v1: f64):
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v2 = fdiv v0, v1
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return v2
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}
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; check: fdiv d0, d0, d1
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; nextln: ret
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function %f9(f32, f32) -> f32 {
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block0(v0: f32, v1: f32):
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v2 = fmin v0, v1
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return v2
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}
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; check: fmin s0, s0, s1
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; nextln: ret
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function %f10(f64, f64) -> f64 {
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block0(v0: f64, v1: f64):
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v2 = fmin v0, v1
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return v2
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}
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; check: fmin d0, d0, d1
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; nextln: ret
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function %f11(f32, f32) -> f32 {
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block0(v0: f32, v1: f32):
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v2 = fmax v0, v1
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return v2
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}
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; check: fmax s0, s0, s1
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; nextln: ret
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function %f12(f64, f64) -> f64 {
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block0(v0: f64, v1: f64):
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v2 = fmax v0, v1
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return v2
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}
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; check: fmax d0, d0, d1
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; nextln: ret
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function %f13(f32) -> f32 {
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block0(v0: f32):
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v1 = sqrt v0
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return v1
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}
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; check: fsqrt s0, s0
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; nextln: ret
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function %f15(f64) -> f64 {
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block0(v0: f64):
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v1 = sqrt v0
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return v1
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}
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; check: fsqrt d0, d0
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; nextln: ret
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function %f16(f32) -> f32 {
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block0(v0: f32):
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v1 = fabs v0
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return v1
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}
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; check: fabs s0, s0
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; nextln: ret
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function %f17(f64) -> f64 {
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block0(v0: f64):
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v1 = fabs v0
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return v1
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}
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; check: fabs d0, d0
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; nextln: ret
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function %f18(f32) -> f32 {
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block0(v0: f32):
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v1 = fneg v0
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return v1
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}
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; check: fneg s0, s0
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; nextln: ret
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function %f19(f64) -> f64 {
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block0(v0: f64):
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v1 = fneg v0
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return v1
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}
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; check: fneg d0, d0
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; nextln: ret
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function %f20(f32) -> f64 {
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block0(v0: f32):
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v1 = fpromote.f64 v0
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return v1
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}
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; check: fcvt d0, s0
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; nextln: ret
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function %f21(f64) -> f32 {
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block0(v0: f64):
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v1 = fdemote.f32 v0
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return v1
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}
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; check: fcvt s0, d0
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; nextln: ret
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function %f22(f32) -> f32 {
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block0(v0: f32):
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v1 = ceil v0
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return v1
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}
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; check: frintp s0, s0
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; nextln: ret
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function %f22(f64) -> f64 {
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block0(v0: f64):
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v1 = ceil v0
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return v1
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}
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; check: frintp d0, d0
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; nextln: ret
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function %f23(f32) -> f32 {
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block0(v0: f32):
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v1 = floor v0
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return v1
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}
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; check: frintm s0, s0
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; nextln: ret
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function %f24(f64) -> f64 {
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block0(v0: f64):
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v1 = floor v0
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return v1
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}
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; check: frintm d0, d0
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; nextln: ret
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function %f25(f32) -> f32 {
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block0(v0: f32):
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v1 = trunc v0
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return v1
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}
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; check: frintz s0, s0
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; nextln: ret
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function %f26(f64) -> f64 {
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block0(v0: f64):
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v1 = trunc v0
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return v1
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}
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; check: frintz d0, d0
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; nextln: ret
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function %f27(f32) -> f32 {
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block0(v0: f32):
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v1 = nearest v0
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return v1
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}
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; check: frintn s0, s0
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; nextln: ret
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function %f28(f64) -> f64 {
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block0(v0: f64):
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v1 = nearest v0
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return v1
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}
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; check: frintn d0, d0
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; nextln: ret
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function %f29(f32, f32, f32) -> f32 {
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block0(v0: f32, v1: f32, v2: f32):
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v3 = fma v0, v1, v2
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return v3
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}
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; check: fmadd s0, s0, s1, s2
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; nextln: ret
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function %f30(f64, f64, f64) -> f64 {
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block0(v0: f64, v1: f64, v2: f64):
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v3 = fma v0, v1, v2
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return v3
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}
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; check: fmadd d0, d0, d1, d2
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; nextln: ret
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function %f31(f32, f32) -> f32 {
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block0(v0: f32, v1: f32):
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v2 = fcopysign v0, v1
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return v2
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}
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; check: ushr v1.2s, v1.2s, #31
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; nextln: sli v0.2s, v1.2s, #31
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; nextln: ret
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function %f32(f64, f64) -> f64 {
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block0(v0: f64, v1: f64):
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v2 = fcopysign v0, v1
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return v2
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}
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; check: ushr d1, d1, #63
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; nextln: sli d0, d1, #63
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; nextln: ret
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function %f33(f32) -> i32 {
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block0(v0: f32):
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v1 = fcvt_to_uint.i32 v0
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return v1
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}
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; check: fcmp s0, s0
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; nextln: b.vc 8 ; udf
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; nextln: movz x0, #49024, LSL #16
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; nextln: fmov d1, x0
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; nextln: fcmp s0, s1
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; nextln: b.gt 8 ; udf
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; nextln: movz x0, #20352, LSL #16
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; nextln: fmov d1, x0
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; nextln: fcmp s0, s1
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; nextln: b.mi 8 ; udf
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; nextln: fcvtzu w0, s0
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; nextln: ret
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function %f34(f32) -> i32 {
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block0(v0: f32):
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v1 = fcvt_to_sint.i32 v0
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return v1
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}
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; check: fcmp s0, s0
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; nextln: b.vc 8 ; udf
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; nextln: movz x0, #52992, LSL #16
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; nextln: fmov d1, x0
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; nextln: fcmp s0, s1
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; nextln: b.ge 8 ; udf
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; nextln: movz x0, #20224, LSL #16
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; nextln: fmov d1, x0
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; nextln: fcmp s0, s1
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; nextln: b.mi 8 ; udf
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; nextln: fcvtzs w0, s0
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; nextln: ret
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function %f35(f32) -> i64 {
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block0(v0: f32):
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v1 = fcvt_to_uint.i64 v0
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return v1
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}
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; check: fcmp s0, s0
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; nextln: b.vc 8 ; udf
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; nextln: movz x0, #49024, LSL #16
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; nextln: fmov d1, x0
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; nextln: fcmp s0, s1
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; nextln: b.gt 8 ; udf
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; nextln: movz x0, #24448, LSL #16
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; nextln: fmov d1, x0
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; nextln: fcmp s0, s1
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; nextln: b.mi 8 ; udf
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; nextln: fcvtzu x0, s0
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; nextln: ret
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function %f36(f32) -> i64 {
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block0(v0: f32):
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v1 = fcvt_to_sint.i64 v0
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return v1
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}
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; check: fcmp s0, s0
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; nextln: b.vc 8 ; udf
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; nextln: movz x0, #57088, LSL #16
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; nextln: fmov d1, x0
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; nextln: fcmp s0, s1
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; nextln: b.ge 8 ; udf
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; nextln: movz x0, #24320, LSL #16
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; nextln: fmov d1, x0
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; nextln: fcmp s0, s1
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; nextln: b.mi 8 ; udf
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; nextln: fcvtzs x0, s0
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; nextln: ret
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function %f37(f64) -> i32 {
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block0(v0: f64):
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v1 = fcvt_to_uint.i32 v0
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return v1
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}
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; check: fcmp d0, d0
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; nextln: b.vc 8 ; udf
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; nextln: movz x0, #49136, LSL #48
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; nextln: fmov d1, x0
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; nextln: fcmp d0, d1
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; nextln: b.gt 8 ; udf
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; nextln: movz x0, #16880, LSL #48
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; nextln: fmov d1, x0
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; nextln: fcmp d0, d1
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; nextln: b.mi 8 ; udf
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; nextln: fcvtzu w0, d0
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; nextln: ret
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function %f38(f64) -> i32 {
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block0(v0: f64):
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v1 = fcvt_to_sint.i32 v0
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return v1
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}
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; check: fcmp d0, d0
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; nextln: b.vc 8 ; udf
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; nextln: ldr d1, pc+8 ; b 12 ; data.f64 -2147483649
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; nextln: fcmp d0, d1
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; nextln: b.gt 8 ; udf
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; nextln: movz x0, #16864, LSL #48
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; nextln: fmov d1, x0
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; nextln: fcmp d0, d1
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; nextln: b.mi 8 ; udf
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; nextln: fcvtzs w0, d0
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; nextln: ret
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function %f39(f64) -> i64 {
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block0(v0: f64):
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v1 = fcvt_to_uint.i64 v0
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return v1
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}
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; check: fcmp d0, d0
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; nextln: b.vc 8 ; udf
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; nextln: movz x0, #49136, LSL #48
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; nextln: fmov d1, x0
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; nextln: fcmp d0, d1
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; nextln: b.gt 8 ; udf
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; nextln: movz x0, #17392, LSL #48
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; nextln: fmov d1, x0
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; nextln: fcmp d0, d1
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; nextln: b.mi 8 ; udf
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; nextln: fcvtzu x0, d0
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; nextln: ret
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function %f40(f64) -> i64 {
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block0(v0: f64):
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v1 = fcvt_to_sint.i64 v0
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return v1
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}
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; check: fcmp d0, d0
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; nextln: b.vc 8 ; udf
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; nextln: movz x0, #50144, LSL #48
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; nextln: fmov d1, x0
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; nextln: fcmp d0, d1
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; nextln: b.ge 8 ; udf
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; nextln: movz x0, #17376, LSL #48
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; nextln: fmov d1, x0
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; nextln: fcmp d0, d1
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; nextln: b.mi 8 ; udf
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; nextln: fcvtzs x0, d0
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; nextln: ret
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function %f41(i32) -> f32 {
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block0(v0: i32):
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v1 = fcvt_from_uint.f32 v0
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return v1
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}
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; check: ucvtf s0, w0
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; nextln: ret
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function %f42(i32) -> f32 {
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block0(v0: i32):
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v1 = fcvt_from_sint.f32 v0
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return v1
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}
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; check: scvtf s0, w0
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; nextln: ret
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function %f43(i64) -> f32 {
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block0(v0: i64):
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v1 = fcvt_from_uint.f32 v0
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return v1
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}
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; check: ucvtf s0, x0
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; nextln: ret
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function %f44(i64) -> f32 {
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block0(v0: i64):
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v1 = fcvt_from_sint.f32 v0
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return v1
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}
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; check: scvtf s0, x0
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; nextln: ret
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function %f45(i32) -> f64 {
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block0(v0: i32):
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v1 = fcvt_from_uint.f64 v0
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return v1
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}
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; check: ucvtf d0, w0
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; nextln: ret
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function %f46(i32) -> f64 {
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block0(v0: i32):
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v1 = fcvt_from_sint.f64 v0
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return v1
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}
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; check: scvtf d0, w0
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; nextln: ret
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function %f47(i64) -> f64 {
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block0(v0: i64):
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v1 = fcvt_from_uint.f64 v0
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return v1
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}
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; check: ucvtf d0, x0
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; nextln: ret
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function %f48(i64) -> f64 {
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block0(v0: i64):
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v1 = fcvt_from_sint.f64 v0
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return v1
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}
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; check: scvtf d0, x0
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; nextln: ret
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function %f49(f32) -> i32 {
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block0(v0: f32):
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v1 = fcvt_to_uint_sat.i32 v0
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return v1
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}
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; check: movz x0, #20352, LSL #16
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; nextln: fmov d1, x0
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; nextln: fmin s2, s0, s1
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; nextln: movi v1.2s, #0
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; nextln: fmax s2, s2, s1
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; nextln: fcmp s0, s0
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; nextln: fcsel s0, s1, s2, ne
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; nextln: fcvtzu w0, s0
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; nextln: ret
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function %f50(f32) -> i32 {
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block0(v0: f32):
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v1 = fcvt_to_sint_sat.i32 v0
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return v1
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}
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; check: movz x0, #20224, LSL #16
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; nextln: fmov d1, x0
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; nextln: fmin s1, s0, s1
|
|
; nextln: movz x0, #52992, LSL #16
|
|
; nextln: fmov d2, x0
|
|
; nextln: fmax s1, s1, s2
|
|
; nextln: movi v2.2s, #0
|
|
; nextln: fcmp s0, s0
|
|
; nextln: fcsel s0, s2, s1, ne
|
|
; nextln: fcvtzs w0, s0
|
|
; nextln: ret
|
|
|
|
function %f51(f32) -> i64 {
|
|
block0(v0: f32):
|
|
v1 = fcvt_to_uint_sat.i64 v0
|
|
return v1
|
|
}
|
|
|
|
; check: movz x0, #24448, LSL #16
|
|
; nextln: fmov d1, x0
|
|
; nextln: fmin s2, s0, s1
|
|
; nextln: movi v1.2s, #0
|
|
; nextln: fmax s2, s2, s1
|
|
; nextln: fcmp s0, s0
|
|
; nextln: fcsel s0, s1, s2, ne
|
|
; nextln: fcvtzu x0, s0
|
|
; nextln: ret
|
|
|
|
function %f52(f32) -> i64 {
|
|
block0(v0: f32):
|
|
v1 = fcvt_to_sint_sat.i64 v0
|
|
return v1
|
|
}
|
|
|
|
; check: movz x0, #24320, LSL #16
|
|
; nextln: fmov d1, x0
|
|
; nextln: fmin s1, s0, s1
|
|
; nextln: movz x0, #57088, LSL #16
|
|
; nextln: fmov d2, x0
|
|
; nextln: fmax s1, s1, s2
|
|
; nextln: movi v2.2s, #0
|
|
; nextln: fcmp s0, s0
|
|
; nextln: fcsel s0, s2, s1, ne
|
|
; nextln: fcvtzs x0, s0
|
|
; nextln: ret
|
|
|
|
function %f53(f64) -> i32 {
|
|
block0(v0: f64):
|
|
v1 = fcvt_to_uint_sat.i32 v0
|
|
return v1
|
|
}
|
|
|
|
; check: ldr d1, pc+8 ; b 12 ; data.f64 4294967295
|
|
; nextln: fmin d2, d0, d1
|
|
; nextln: movi v1.2s, #0
|
|
; nextln: fmax d2, d2, d1
|
|
; nextln: fcmp d0, d0
|
|
; nextln: fcsel d0, d1, d2, ne
|
|
; nextln: fcvtzu w0, d0
|
|
; nextln: ret
|
|
|
|
function %f54(f64) -> i32 {
|
|
block0(v0: f64):
|
|
v1 = fcvt_to_sint_sat.i32 v0
|
|
return v1
|
|
}
|
|
|
|
; check: ldr d1, pc+8 ; b 12 ; data.f64 2147483647
|
|
; nextln: fmin d1, d0, d1
|
|
; nextln: movz x0, #49632, LSL #48
|
|
; nextln: fmov d2, x0
|
|
; nextln: fmax d1, d1, d2
|
|
; nextln: movi v2.2s, #0
|
|
; nextln: fcmp d0, d0
|
|
; nextln: fcsel d0, d2, d1, ne
|
|
; nextln: fcvtzs w0, d0
|
|
; nextln: ret
|
|
|
|
function %f55(f64) -> i64 {
|
|
block0(v0: f64):
|
|
v1 = fcvt_to_uint_sat.i64 v0
|
|
return v1
|
|
}
|
|
|
|
; check: movz x0, #17392, LSL #48
|
|
; nextln: fmov d1, x0
|
|
; nextln: fmin d2, d0, d1
|
|
; nextln: movi v1.2s, #0
|
|
; nextln: fmax d2, d2, d1
|
|
; nextln: fcmp d0, d0
|
|
; nextln: fcsel d0, d1, d2, ne
|
|
; nextln: fcvtzu x0, d0
|
|
; nextln: ret
|
|
|
|
function %f56(f64) -> i64 {
|
|
block0(v0: f64):
|
|
v1 = fcvt_to_sint_sat.i64 v0
|
|
return v1
|
|
}
|
|
|
|
; check: movz x0, #17376, LSL #48
|
|
; nextln: fmov d1, x0
|
|
; nextln: fmin d1, d0, d1
|
|
; nextln: movz x0, #50144, LSL #48
|
|
; nextln: fmov d2, x0
|
|
; nextln: fmax d1, d1, d2
|
|
; nextln: movi v2.2s, #0
|
|
; nextln: fcmp d0, d0
|
|
; nextln: fcsel d0, d2, d1, ne
|
|
; nextln: fcvtzs x0, d0
|
|
; nextln: ret
|