79cea5e18b
* Add 'jump_table_entry' and 'indirect_jump' instructions. * Update CodeSink to keep track of code size. Pretty up clif-util's disassembly output. * Only disassemble the machine portion of output. Pretty print the read-only data after it. * Update switch frontend code to use new br_table instruction w/ default.
657 lines
19 KiB
Python
657 lines
19 KiB
Python
"""
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Patterns for legalizing the `base` instruction set.
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The base Cranelift instruction set is 'fat', and many instructions don't have
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legal representations in a given target ISA. This module defines legalization
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patterns that describe how base instructions can be transformed to other base
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instructions that are legal.
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"""
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from __future__ import absolute_import
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from .immediates import intcc, imm64, ieee32, ieee64
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from . import instructions as insts
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from . import types
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from .instructions import uextend, sextend, ireduce
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from .instructions import iadd, iadd_cout, iadd_cin, iadd_carry, iadd_imm
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from .instructions import isub, isub_bin, isub_bout, isub_borrow, irsub_imm
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from .instructions import imul, imul_imm
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from .instructions import sdiv, sdiv_imm, udiv, udiv_imm
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from .instructions import srem, srem_imm, urem, urem_imm
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from .instructions import band, bor, bxor, isplit, iconcat
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from .instructions import bnot, band_not, bor_not, bxor_not
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from .instructions import band_imm, bor_imm, bxor_imm
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from .instructions import icmp, icmp_imm, ifcmp, ifcmp_imm
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from .instructions import iconst, bint, select
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from .instructions import ishl, ishl_imm, sshr, sshr_imm, ushr, ushr_imm
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from .instructions import rotl, rotl_imm, rotr, rotr_imm
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from .instructions import f32const, f64const
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from .instructions import store, load
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from .instructions import br_table
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from .instructions import bitrev
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from cdsl.ast import Var
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from cdsl.xform import Rtl, XFormGroup
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try:
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from typing import TYPE_CHECKING # noqa
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if TYPE_CHECKING:
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from cdsl.instructions import Instruction # noqa
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except ImportError:
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TYPE_CHECKING = False
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narrow = XFormGroup('narrow', """
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Legalize instructions by narrowing.
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The transformations in the 'narrow' group work by expressing
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instructions in terms of smaller types. Operations on vector types are
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expressed in terms of vector types with fewer lanes, and integer
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operations are expressed in terms of smaller integer types.
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""")
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widen = XFormGroup('widen', """
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Legalize instructions by widening.
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The transformations in the 'widen' group work by expressing
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instructions in terms of larger types.
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""")
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expand = XFormGroup('expand', """
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Legalize instructions by expansion.
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Rewrite instructions in terms of other instructions, generally
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operating on the same types as the original instructions.
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""")
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expand_flags = XFormGroup('expand_flags', """
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Instruction expansions for architectures with flags.
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Expand some instructions using CPU flags, then fall back to the normal
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expansions. Not all architectures support CPU flags, so these patterns
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are kept separate.
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""", chain=expand)
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# Custom expansions for memory objects.
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expand.custom_legalize(insts.global_value, 'expand_global_value')
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expand.custom_legalize(insts.heap_addr, 'expand_heap_addr')
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expand.custom_legalize(insts.table_addr, 'expand_table_addr')
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# Custom expansions for calls.
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expand.custom_legalize(insts.call, 'expand_call')
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# Custom expansions that need to change the CFG.
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# TODO: Add sufficient XForm syntax that we don't need to hand-code these.
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expand.custom_legalize(insts.trapz, 'expand_cond_trap')
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expand.custom_legalize(insts.trapnz, 'expand_cond_trap')
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expand.custom_legalize(insts.br_table, 'expand_br_table')
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expand.custom_legalize(insts.select, 'expand_select')
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# Custom expansions for floating point constants.
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# These expansions require bit-casting or creating constant pool entries.
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expand.custom_legalize(insts.f32const, 'expand_fconst')
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expand.custom_legalize(insts.f64const, 'expand_fconst')
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# Custom expansions for stack memory accesses.
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expand.custom_legalize(insts.stack_load, 'expand_stack_load')
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expand.custom_legalize(insts.stack_store, 'expand_stack_store')
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x = Var('x')
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y = Var('y')
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z = Var('z')
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a = Var('a')
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a1 = Var('a1')
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a2 = Var('a2')
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a3 = Var('a3')
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a4 = Var('a4')
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b = Var('b')
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b1 = Var('b1')
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b2 = Var('b2')
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b3 = Var('b3')
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b4 = Var('b4')
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b_in = Var('b_in')
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b_int = Var('b_int')
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c = Var('c')
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c1 = Var('c1')
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c2 = Var('c2')
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c3 = Var('c3')
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c4 = Var('c4')
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c_in = Var('c_in')
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c_int = Var('c_int')
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d = Var('d')
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d1 = Var('d1')
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d2 = Var('d2')
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d3 = Var('d3')
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d4 = Var('d4')
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e = Var('e')
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e1 = Var('e1')
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e2 = Var('e2')
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e3 = Var('e3')
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e4 = Var('e4')
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f = Var('f')
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f1 = Var('f1')
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f2 = Var('f2')
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xl = Var('xl')
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xh = Var('xh')
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yl = Var('yl')
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yh = Var('yh')
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al = Var('al')
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ah = Var('ah')
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cc = Var('cc')
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ptr = Var('ptr')
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flags = Var('flags')
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offset = Var('off')
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ss = Var('ss')
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narrow.legalize(
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a << iadd(x, y),
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Rtl(
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(xl, xh) << isplit(x),
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(yl, yh) << isplit(y),
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(al, c) << iadd_cout(xl, yl),
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ah << iadd_cin(xh, yh, c),
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a << iconcat(al, ah)
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))
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narrow.legalize(
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a << isub(x, y),
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Rtl(
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(xl, xh) << isplit(x),
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(yl, yh) << isplit(y),
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(al, b) << isub_bout(xl, yl),
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ah << isub_bin(xh, yh, b),
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a << iconcat(al, ah)
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))
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for bitop in [band, bor, bxor]:
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narrow.legalize(
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a << bitop(x, y),
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Rtl(
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(xl, xh) << isplit(x),
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(yl, yh) << isplit(y),
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al << bitop(xl, yl),
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ah << bitop(xh, yh),
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a << iconcat(al, ah)
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))
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narrow.legalize(
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a << select(c, x, y),
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Rtl(
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(xl, xh) << isplit(x),
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(yl, yh) << isplit(y),
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al << select(c, xl, yl),
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ah << select(c, xh, yh),
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a << iconcat(al, ah)
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))
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def widen_one_arg(signed, op):
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# type: (bool, Instruction) -> None
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for int_ty in [types.i8, types.i16]:
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if signed:
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widen.legalize(
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a << op.bind(int_ty)(b),
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Rtl(
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x << sextend.i32(b),
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z << op.i32(x),
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a << ireduce.bind(int_ty)(z)
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))
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else:
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widen.legalize(
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a << op.bind(int_ty)(b),
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Rtl(
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x << uextend.i32(b),
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z << op.i32(x),
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a << ireduce.bind(int_ty)(z)
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))
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def widen_two_arg(signed, op):
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# type: (bool, Instruction) -> None
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for int_ty in [types.i8, types.i16]:
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if signed:
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widen.legalize(
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a << op.bind(int_ty)(b, c),
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Rtl(
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x << sextend.i32(b),
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y << sextend.i32(c),
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z << op.i32(x, y),
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a << ireduce.bind(int_ty)(z)
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))
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else:
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widen.legalize(
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a << op.bind(int_ty)(b, c),
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Rtl(
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x << uextend.i32(b),
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y << uextend.i32(c),
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z << op.i32(x, y),
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a << ireduce.bind(int_ty)(z)
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))
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def widen_imm(signed, op):
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# type: (bool, Instruction) -> None
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for int_ty in [types.i8, types.i16]:
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if signed:
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widen.legalize(
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a << op.bind(int_ty)(b, c),
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Rtl(
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x << sextend.i32(b),
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z << op.i32(x, c),
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a << ireduce.bind(int_ty)(z)
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))
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else:
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widen.legalize(
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a << op.bind(int_ty)(b, c),
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Rtl(
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x << uextend.i32(b),
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z << op.i32(x, c),
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a << ireduce.bind(int_ty)(z)
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))
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for binop in [iadd, isub, imul, udiv, urem]:
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widen_two_arg(False, binop)
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widen_two_arg(True, sdiv)
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widen_one_arg(False, bnot)
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for binop in [iadd_imm, imul_imm, udiv_imm, urem_imm]:
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widen_imm(False, binop)
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for binop in [sdiv_imm, srem_imm]:
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widen_imm(True, binop)
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# bit ops
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for binop in [band, bor, bxor, band_not, bor_not, bxor_not]:
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widen_two_arg(False, binop)
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for binop in [band_imm, bor_imm, bxor_imm]:
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widen_imm(False, binop)
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for int_ty in [types.i8, types.i16]:
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widen.legalize(
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a << iconst.bind(int_ty)(b),
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Rtl(
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c << iconst.i32(b),
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a << ireduce.bind(int_ty)(c)
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))
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widen.legalize(
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store.i8(flags, a, ptr, offset),
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Rtl(
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b << uextend.i32(a),
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insts.istore8(flags, b, ptr, offset)
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))
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widen.legalize(
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store.i16(flags, a, ptr, offset),
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Rtl(
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b << uextend.i32(a),
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insts.istore16(flags, b, ptr, offset)
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))
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widen.legalize(
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a << load.i8(flags, ptr, offset),
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Rtl(
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b << insts.uload8.i32(flags, ptr, offset),
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a << ireduce(b)
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))
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widen.legalize(
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a << load.i16(flags, ptr, offset),
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Rtl(
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b << insts.uload16.i32(flags, ptr, offset),
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a << ireduce(b)
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))
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for int_ty in [types.i8, types.i16]:
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widen.legalize(
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br_table.bind(int_ty)(x, y, z),
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Rtl(
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b << uextend.i32(x),
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br_table(b, y, z),
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)
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)
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for int_ty in [types.i8, types.i16]:
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widen.legalize(
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a << insts.bint.bind(int_ty)(b),
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Rtl(
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x << insts.bint.i32(b),
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a << ireduce.bind(int_ty)(x)
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)
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)
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for int_ty in [types.i8, types.i16]:
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for op in [ushr_imm, ishl_imm]:
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widen.legalize(
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a << op.bind(int_ty)(b, c),
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Rtl(
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x << uextend.i32(b),
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z << op.i32(x, c),
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a << ireduce.bind(int_ty)(z)
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))
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widen.legalize(
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a << ishl.bind(int_ty)(b, c),
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Rtl(
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x << uextend.i32(b),
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z << ishl.i32(x, c),
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a << ireduce.bind(int_ty)(z)
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))
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widen.legalize(
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a << ushr.bind(int_ty)(b, c),
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Rtl(
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x << uextend.i32(b),
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z << ushr.i32(x, c),
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a << ireduce.bind(int_ty)(z)
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))
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widen.legalize(
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a << sshr.bind(int_ty)(b, c),
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Rtl(
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x << sextend.i32(b),
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z << sshr.i32(x, c),
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a << ireduce.bind(int_ty)(z)
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))
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for w_cc in [
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intcc.eq, intcc.ne, intcc.ugt, intcc.ult, intcc.uge, intcc.ule
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]:
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widen.legalize(
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a << insts.icmp_imm.bind(int_ty)(w_cc, b, c),
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Rtl(
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x << uextend.i32(b),
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a << insts.icmp_imm(w_cc, x, c)
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))
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widen.legalize(
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a << insts.icmp.bind(int_ty)(w_cc, b, c),
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Rtl(
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x << uextend.i32(b),
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y << uextend.i32(c),
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a << insts.icmp.i32(w_cc, x, y)
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))
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for w_cc in [intcc.sgt, intcc.slt, intcc.sge, intcc.sle]:
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widen.legalize(
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a << insts.icmp_imm.bind(int_ty)(w_cc, b, c),
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Rtl(
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x << sextend.i32(b),
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a << insts.icmp_imm(w_cc, x, c)
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))
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widen.legalize(
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a << insts.icmp.bind(int_ty)(w_cc, b, c),
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Rtl(
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x << sextend.i32(b),
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y << sextend.i32(c),
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a << insts.icmp(w_cc, x, y)
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)
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)
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# Expand integer operations with carry for RISC architectures that don't have
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# the flags.
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expand.legalize(
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(a, c) << iadd_cout(x, y),
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Rtl(
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a << iadd(x, y),
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c << icmp(intcc.ult, a, x)
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))
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expand.legalize(
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(a, b) << isub_bout(x, y),
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Rtl(
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a << isub(x, y),
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b << icmp(intcc.ugt, a, x)
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))
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expand.legalize(
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a << iadd_cin(x, y, c),
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Rtl(
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a1 << iadd(x, y),
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c_int << bint(c),
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a << iadd(a1, c_int)
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))
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expand.legalize(
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a << isub_bin(x, y, b),
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Rtl(
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a1 << isub(x, y),
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b_int << bint(b),
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a << isub(a1, b_int)
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))
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expand.legalize(
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(a, c) << iadd_carry(x, y, c_in),
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Rtl(
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(a1, c1) << iadd_cout(x, y),
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c_int << bint(c_in),
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(a, c2) << iadd_cout(a1, c_int),
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c << bor(c1, c2)
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))
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expand.legalize(
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|
(a, b) << isub_borrow(x, y, b_in),
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Rtl(
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(a1, b1) << isub_bout(x, y),
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|
b_int << bint(b_in),
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|
(a, b2) << isub_bout(a1, b_int),
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b << bor(b1, b2)
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))
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|
# Expansions for immediate operands that are out of range.
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|
for inst_imm, inst in [
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(iadd_imm, iadd),
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(imul_imm, imul),
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(sdiv_imm, sdiv),
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|
(udiv_imm, udiv),
|
|
(srem_imm, srem),
|
|
(urem_imm, urem),
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|
(band_imm, band),
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|
(bor_imm, bor),
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|
(bxor_imm, bor),
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|
(ifcmp_imm, ifcmp)]:
|
|
expand.legalize(
|
|
a << inst_imm(x, y),
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|
Rtl(
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|
a1 << iconst(y),
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|
a << inst(x, a1)
|
|
))
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|
expand.legalize(
|
|
a << irsub_imm(y, x),
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|
Rtl(
|
|
a1 << iconst(x),
|
|
a << isub(a1, y)
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|
))
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|
|
|
# Rotates and shifts.
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|
for inst_imm, inst in [
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(rotl_imm, rotl),
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(rotr_imm, rotr),
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|
(ishl_imm, ishl),
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|
(sshr_imm, sshr),
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|
(ushr_imm, ushr)]:
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|
expand.legalize(
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|
a << inst_imm(x, y),
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|
Rtl(
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|
a1 << iconst.i32(y),
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|
a << inst(x, a1)
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|
))
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|
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|
expand.legalize(
|
|
a << icmp_imm(cc, x, y),
|
|
Rtl(
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|
a1 << iconst(y),
|
|
a << icmp(cc, x, a1)
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|
))
|
|
|
|
# Expansions for *_not variants of bitwise ops.
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|
for inst_not, inst in [
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|
(band_not, band),
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|
(bor_not, bor),
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(bxor_not, bxor)]:
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|
expand.legalize(
|
|
a << inst_not(x, y),
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|
Rtl(
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a1 << bnot(y),
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a << inst(x, a1)
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))
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|
# Expand bnot using xor.
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|
expand.legalize(
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|
a << bnot(x),
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|
Rtl(
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|
y << iconst(imm64(-1)),
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|
a << bxor(x, y)
|
|
))
|
|
|
|
# Expand bitrev
|
|
# Adapted from Stack Overflow.
|
|
# https://stackoverflow.com/questions/746171/most-efficient-algorithm-for-bit-reversal-from-msb-lsb-to-lsb-msb-in-c
|
|
widen.legalize(
|
|
a << bitrev.i8(x),
|
|
Rtl(
|
|
a1 << band_imm(x, imm64(0xaa)),
|
|
a2 << ushr_imm(a1, imm64(1)),
|
|
a3 << band_imm(x, imm64(0x55)),
|
|
a4 << ishl_imm(a3, imm64(1)),
|
|
b << bor(a2, a4),
|
|
b1 << band_imm(b, imm64(0xcc)),
|
|
b2 << ushr_imm(b1, imm64(2)),
|
|
b3 << band_imm(b, imm64(0x33)),
|
|
b4 << ushr_imm(b3, imm64(2)),
|
|
c << bor(b2, b4),
|
|
c1 << band_imm(c, imm64(0xf0)),
|
|
c2 << ushr_imm(c1, imm64(4)),
|
|
c3 << band_imm(c, imm64(0x0f)),
|
|
c4 << ishl_imm(c3, imm64(4)),
|
|
a << bor(c2, c4),
|
|
))
|
|
|
|
widen.legalize(
|
|
a << bitrev.i16(x),
|
|
Rtl(
|
|
a1 << band_imm(x, imm64(0xaaaa)),
|
|
a2 << ushr_imm(a1, imm64(1)),
|
|
a3 << band_imm(x, imm64(0x5555)),
|
|
a4 << ishl_imm(a3, imm64(1)),
|
|
b << bor(a2, a4),
|
|
b1 << band_imm(b, imm64(0xcccc)),
|
|
b2 << ushr_imm(b1, imm64(2)),
|
|
b3 << band_imm(b, imm64(0x3333)),
|
|
b4 << ushr_imm(b3, imm64(2)),
|
|
c << bor(b2, b4),
|
|
c1 << band_imm(c, imm64(0xf0f0)),
|
|
c2 << ushr_imm(c1, imm64(4)),
|
|
c3 << band_imm(c, imm64(0x0f0f)),
|
|
c4 << ishl_imm(c3, imm64(4)),
|
|
d << bor(c2, c4),
|
|
d1 << band_imm(d, imm64(0xff00)),
|
|
d2 << ushr_imm(d1, imm64(8)),
|
|
d3 << band_imm(d, imm64(0x00ff)),
|
|
d4 << ishl_imm(d3, imm64(8)),
|
|
a << bor(d2, d4),
|
|
))
|
|
|
|
expand.legalize(
|
|
a << bitrev.i32(x),
|
|
Rtl(
|
|
a1 << band_imm(x, imm64(0xaaaaaaaa)),
|
|
a2 << ushr_imm(a1, imm64(1)),
|
|
a3 << band_imm(x, imm64(0x55555555)),
|
|
a4 << ishl_imm(a3, imm64(1)),
|
|
b << bor(a2, a4),
|
|
b1 << band_imm(b, imm64(0xcccccccc)),
|
|
b2 << ushr_imm(b1, imm64(2)),
|
|
b3 << band_imm(b, imm64(0x33333333)),
|
|
b4 << ushr_imm(b3, imm64(2)),
|
|
c << bor(b2, b4),
|
|
c1 << band_imm(c, imm64(0xf0f0f0f0)),
|
|
c2 << ushr_imm(c1, imm64(4)),
|
|
c3 << band_imm(c, imm64(0x0f0f0f0f)),
|
|
c4 << ishl_imm(c3, imm64(4)),
|
|
d << bor(c2, c4),
|
|
d1 << band_imm(d, imm64(0xff00ff00)),
|
|
d2 << ushr_imm(d1, imm64(8)),
|
|
d3 << band_imm(d, imm64(0x00ff00ff)),
|
|
d4 << ishl_imm(d3, imm64(8)),
|
|
e << bor(d2, d4),
|
|
e1 << ushr_imm(e, imm64(16)),
|
|
e2 << ishl_imm(e, imm64(16)),
|
|
a << bor(e1, e2),
|
|
))
|
|
|
|
expand.legalize(
|
|
a << bitrev.i64(x),
|
|
Rtl(
|
|
a1 << band_imm(x, imm64(0xaaaaaaaaaaaaaaaa)),
|
|
a2 << ushr_imm(a1, imm64(1)),
|
|
a3 << band_imm(x, imm64(0x5555555555555555)),
|
|
a4 << ishl_imm(a3, imm64(1)),
|
|
b << bor(a2, a4),
|
|
b1 << band_imm(b, imm64(0xcccccccccccccccc)),
|
|
b2 << ushr_imm(b1, imm64(2)),
|
|
b3 << band_imm(b, imm64(0x3333333333333333)),
|
|
b4 << ushr_imm(b3, imm64(2)),
|
|
c << bor(b2, b4),
|
|
c1 << band_imm(c, imm64(0xf0f0f0f0f0f0f0f0)),
|
|
c2 << ushr_imm(c1, imm64(4)),
|
|
c3 << band_imm(c, imm64(0x0f0f0f0f0f0f0f0f)),
|
|
c4 << ishl_imm(c3, imm64(4)),
|
|
d << bor(c2, c4),
|
|
d1 << band_imm(d, imm64(0xff00ff00ff00ff00)),
|
|
d2 << ushr_imm(d1, imm64(8)),
|
|
d3 << band_imm(d, imm64(0x00ff00ff00ff00ff)),
|
|
d4 << ishl_imm(d3, imm64(8)),
|
|
e << bor(d2, d4),
|
|
e1 << band_imm(e, imm64(0xffff0000ffff0000)),
|
|
e2 << ushr_imm(e1, imm64(16)),
|
|
e3 << band_imm(e, imm64(0x0000ffff0000ffff)),
|
|
e4 << ishl_imm(e3, imm64(16)),
|
|
f << bor(e2, e4),
|
|
f1 << ushr_imm(f, imm64(32)),
|
|
f2 << ishl_imm(f, imm64(32)),
|
|
a << bor(f1, f2),
|
|
))
|
|
|
|
# Floating-point sign manipulations.
|
|
for ty, minus_zero in [
|
|
(types.f32, f32const(ieee32.bits(0x80000000))),
|
|
(types.f64, f64const(ieee64.bits(0x8000000000000000)))]:
|
|
expand.legalize(
|
|
a << insts.fabs.bind(ty)(x),
|
|
Rtl(
|
|
b << minus_zero,
|
|
a << band_not(x, b),
|
|
))
|
|
expand.legalize(
|
|
a << insts.fneg.bind(ty)(x),
|
|
Rtl(
|
|
b << minus_zero,
|
|
a << bxor(x, b),
|
|
))
|
|
expand.legalize(
|
|
a << insts.fcopysign.bind(ty)(x, y),
|
|
Rtl(
|
|
b << minus_zero,
|
|
a1 << band_not(x, b),
|
|
a2 << band(y, b),
|
|
a << bor(a1, a2)
|
|
))
|
|
|
|
expand.custom_legalize(insts.br_icmp, 'expand_br_icmp')
|
|
|
|
# Expansions using CPU flags.
|
|
|
|
expand_flags.legalize(
|
|
insts.trapnz(x, c),
|
|
Rtl(
|
|
a << insts.ifcmp_imm(x, imm64(0)),
|
|
insts.trapif(intcc.ne, a, c)
|
|
))
|
|
expand_flags.legalize(
|
|
insts.trapz(x, c),
|
|
Rtl(
|
|
a << insts.ifcmp_imm(x, imm64(0)),
|
|
insts.trapif(intcc.eq, a, c)
|
|
))
|