83c3bc5b9d
Implemented the following Opcodes for the Cranelift interpreter: - `Unarrow` to combine two SIMD vectors into a new vector with twice the lanes but half the width, with signed inputs which are clamped to `0x00`. - `Uunarrow` to perform the same operation as `Unarrow` but treating inputs as unsigned. - `Snarrow` to perform the same operation as `Unarrow` but treating both inputs and outputs as signed, and saturating accordingly. Note that all 3 instructions saturate at the type boundaries. Copyright (c) 2021, Arm Limited
27 lines
954 B
Plaintext
27 lines
954 B
Plaintext
test interpret
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test run
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target aarch64
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; x86_64 panics: `Did not match fcvt input!
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; thread 'worker #0' panicked at 'register allocation: Analysis(EntryLiveinValues([v2V]))', cranelift/codegen/src/machinst/compile.rs:96:10`
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function %uunarrow_i16x8(i16x8, i16x8) -> i8x16 {
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block0(v0: i16x8, v1: i16x8):
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v2 = uunarrow v0, v1
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return v2
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}
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; run: %uunarrow_i16x8([1 127 128 15 65535 -32 48 0], [8 255 -100 100 65534 73 80 42]) == [1 127 128 15 255 255 48 0 8 255 255 100 255 73 80 42]
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function %uunarrow_i32x4(i32x4, i32x4) -> i16x8 {
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block0(v0: i32x4, v1: i32x4):
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v2 = uunarrow v0, v1
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return v2
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}
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; run: %uunarrow_i32x4([65535 1048575 -70000 -5], [268435455 73 268435455 42]) == [65535 65535 65535 65535 65535 73 65535 42]
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function %uunarrow_i64x2(i64x2, i64x2) -> i32x4 {
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block0(v0: i64x2, v1: i64x2):
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v2 = uunarrow v0, v1
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return v2
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}
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; run: %uunarrow_i64x2([65535 -100000], [5000000000 73]) == [65535 4294967295 4294967295 73]
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