82494661c1
* cranelift: Add `fence` to interpreter
* cranelift: Add `atomic_{load,store}` to the interpreter
* fuzzgen: Add `atomic_{load,store}`
* Update cranelift/fuzzgen/src/function_generator.rs
Co-authored-by: Jamey Sharp <jamey@minilop.net>
* fuzzgen: Use type size as the alignment size.
Co-authored-by: Jamey Sharp <jamey@minilop.net>
95 lines
2.8 KiB
Plaintext
95 lines
2.8 KiB
Plaintext
test interpret
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test run
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target x86_64
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target aarch64
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target riscv64
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target s390x
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function %i64_atomic_store_load(i64) -> i64 {
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ss0 = explicit_slot 8
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block0(v0: i64):
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v1 = stack_addr.i64 ss0
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atomic_store.i64 v0, v1
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v2 = atomic_load.i64 v1
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return v2
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}
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; run: %i64_atomic_store_load(0) == 0
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; run: %i64_atomic_store_load(-1) == -1
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; run: %i64_atomic_store_load(0x00000000_FFFFFFFF) == 0x00000000_FFFFFFFF
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; run: %i64_atomic_store_load(0xFFFFFFFF_00000000) == 0xFFFFFFFF_00000000
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; run: %i64_atomic_store_load(0xFEDCBA98_76543210) == 0xFEDCBA98_76543210
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; run: %i64_atomic_store_load(0xA00A00A0_0A00A00A) == 0xA00A00A0_0A00A00A
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; run: %i64_atomic_store_load(0xC0FFEEEE_DECAFFFF) == 0xC0FFEEEE_DECAFFFF
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function %i32_atomic_store_load(i32) -> i32 {
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ss0 = explicit_slot 4
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block0(v0: i32):
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v1 = stack_addr.i64 ss0
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atomic_store.i32 v0, v1
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v2 = atomic_load.i32 v1
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return v2
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}
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; run: %i32_atomic_store_load(0) == 0
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; run: %i32_atomic_store_load(-1) == -1
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; run: %i32_atomic_store_load(0x0000FFFF) == 0x0000FFFF
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; run: %i32_atomic_store_load(0xFFFF0000) == 0xFFFF0000
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; run: %i32_atomic_store_load(0xFEDC3210) == 0xFEDC3210
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; run: %i32_atomic_store_load(0xA00AA00A) == 0xA00AA00A
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; run: %i32_atomic_store_load(0xC0FFEEEE) == 0xC0FFEEEE
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function %i16_atomic_store_load(i16) -> i16 {
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ss0 = explicit_slot 2
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block0(v0: i16):
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v1 = stack_addr.i64 ss0
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atomic_store.i16 v0, v1
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v2 = atomic_load.i16 v1
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return v2
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}
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; run: %i16_atomic_store_load(0) == 0
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; run: %i16_atomic_store_load(-1) == -1
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; run: %i16_atomic_store_load(0x00FF) == 0x00FF
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; run: %i16_atomic_store_load(0xFF00) == 0xFF00
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; run: %i16_atomic_store_load(0xFE10) == 0xFE10
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; run: %i16_atomic_store_load(0xA00A) == 0xA00A
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; run: %i16_atomic_store_load(0xC0FF) == 0xC0FF
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function %i8_atomic_store_load(i8) -> i8 {
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ss0 = explicit_slot 1
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block0(v0: i8):
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v1 = stack_addr.i64 ss0
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atomic_store.i8 v0, v1
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v2 = atomic_load.i8 v1
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return v2
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}
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; run: %i8_atomic_store_load(0) == 0
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; run: %i8_atomic_store_load(-1) == -1
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; run: %i8_atomic_store_load(0x0F) == 0x0F
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; run: %i8_atomic_store_load(0xF0) == 0xF0
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; run: %i8_atomic_store_load(0xAA) == 0xAA
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; run: %i8_atomic_store_load(0xC0) == 0xC0
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function %atomic_store_load_aligned(i64) -> i64 {
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ss0 = explicit_slot 16
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block0(v0: i64):
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v1 = stack_addr.i64 ss0
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atomic_store.i64 aligned v0, v1
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v2 = atomic_load.i64 aligned v1
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return v2
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}
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; run: %atomic_store_load_aligned(0) == 0
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; run: %atomic_store_load_aligned(-1) == -1
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; run: %atomic_store_load_aligned(0x00000000_FFFFFFFF) == 0x00000000_FFFFFFFF
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; run: %atomic_store_load_aligned(0xFFFFFFFF_00000000) == 0xFFFFFFFF_00000000
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; run: %atomic_store_load_aligned(0xFEDCBA98_76543210) == 0xFEDCBA98_76543210
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; run: %atomic_store_load_aligned(0xA00A00A0_0A00A00A) == 0xA00A00A0_0A00A00A
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; run: %atomic_store_load_aligned(0xC0FFEEEE_DECAFFFF) == 0xC0FFEEEE_DECAFFFF
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