129 lines
4.2 KiB
Rust
129 lines
4.2 KiB
Rust
//! ARM ABI implementation.
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use super::registers::{D, GPR, Q, S};
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use crate::abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};
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use crate::ir::{self, AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose, Type};
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use crate::isa::RegClass;
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use crate::regalloc::RegisterSet;
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use core::i32;
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use target_lexicon::Triple;
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struct Args {
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pointer_bits: u8,
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pointer_bytes: u8,
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pointer_type: Type,
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regs: u32,
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reg_limit: u32,
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offset: u32,
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}
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impl Args {
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fn new(bits: u8) -> Self {
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Self {
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pointer_bits: bits,
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pointer_bytes: bits / 8,
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pointer_type: Type::int(u16::from(bits)).unwrap(),
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regs: 0,
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reg_limit: 8,
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offset: 0,
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}
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}
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}
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impl ArgAssigner for Args {
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fn assign(&mut self, arg: &AbiParam) -> ArgAction {
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fn align(value: u32, to: u32) -> u32 {
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(value + to - 1) & !(to - 1)
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}
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let ty = arg.value_type;
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// Check for a legal type.
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// RISC-V doesn't have SIMD at all, so break all vectors down.
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if ty.is_vector() {
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return ValueConversion::VectorSplit.into();
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}
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// Large integers and booleans are broken down to fit in a register.
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if !ty.is_float() && ty.bits() > u16::from(self.pointer_bits) {
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// Align registers and stack to a multiple of two pointers.
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self.regs = align(self.regs, 2);
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self.offset = align(self.offset, 2 * u32::from(self.pointer_bytes));
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return ValueConversion::IntSplit.into();
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}
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// Small integers are extended to the size of a pointer register.
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if ty.is_int() && ty.bits() < u16::from(self.pointer_bits) {
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match arg.extension {
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ArgumentExtension::None => {}
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ArgumentExtension::Uext => return ValueConversion::Uext(self.pointer_type).into(),
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ArgumentExtension::Sext => return ValueConversion::Sext(self.pointer_type).into(),
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}
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}
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if self.regs < self.reg_limit {
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// Assign to a register.
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let reg = GPR.unit(10 + self.regs as usize);
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self.regs += 1;
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ArgumentLoc::Reg(reg).into()
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} else {
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// Assign a stack location.
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let loc = ArgumentLoc::Stack(self.offset as i32);
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self.offset += u32::from(self.pointer_bytes);
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debug_assert!(self.offset <= i32::MAX as u32);
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loc.into()
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}
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}
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}
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/// Legalize `sig`.
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pub fn legalize_signature(sig: &mut ir::Signature, triple: &Triple, current: bool) {
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let bits = triple.pointer_width().unwrap().bits();
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let mut args = Args::new(bits);
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legalize_args(&mut sig.params, &mut args);
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let mut rets = Args::new(bits);
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legalize_args(&mut sig.returns, &mut rets);
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if current {
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let ptr = Type::int(u16::from(bits)).unwrap();
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// Add the link register as an argument and return value.
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//
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// The `jalr` instruction implementing a return can technically accept the return address
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// in any register, but a micro-architecture with a return address predictor will only
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// recognize it as a return if the address is in `x1`.
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let link = AbiParam::special_reg(ptr, ArgumentPurpose::Link, GPR.unit(1));
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sig.params.push(link);
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sig.returns.push(link);
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}
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}
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/// Get register class for a type appearing in a legalized signature.
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pub fn regclass_for_abi_type(ty: ir::Type) -> RegClass {
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if ty.is_int() {
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GPR
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} else {
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match ty.bits() {
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32 => S,
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64 => D,
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128 => Q,
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_ => panic!("Unexpected {} ABI type for arm32", ty),
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}
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}
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}
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/// Get the set of allocatable registers for `func`.
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pub fn allocatable_registers(_func: &ir::Function) -> RegisterSet {
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let mut regs = RegisterSet::new();
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regs.take(GPR, GPR.unit(0)); // Hard-wired 0.
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// %x1 is the link register which is available for allocation.
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regs.take(GPR, GPR.unit(2)); // Stack pointer.
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regs.take(GPR, GPR.unit(3)); // Global pointer.
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regs.take(GPR, GPR.unit(4)); // Thread pointer.
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// TODO: %x8 is the frame pointer. Reserve it?
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regs
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}
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