71768bb6cf
This PR updates the AArch64 ABI implementation so that it (i) properly respects that v8-v15 inclusive have callee-save lower halves, and caller-save upper halves, by conservatively approximating (to full registers) in the appropriate directions when generating prologue caller-saves and when informing the regalloc of clobbered regs across callsites. In order to prevent saving all of these vector registers in the prologue of every non-leaf function due to the above approximation, this also makes use of a new regalloc.rs feature to exclude call instructions' writes from the clobber set returned by register allocation. This is safe whenever the caller and callee have the same ABI (because anything the callee could clobber, the caller is allowed to clobber as well without saving it in the prologue). Fixes #2254.
122 lines
3.1 KiB
Rust
122 lines
3.1 KiB
Rust
//! 32-bit ARM Instruction Set Architecture.
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use crate::ir::condcodes::IntCC;
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use crate::ir::Function;
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use crate::isa::Builder as IsaBuilder;
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use crate::machinst::{compile, MachBackend, MachCompileResult, TargetIsaAdapter, VCode};
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use crate::result::CodegenResult;
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use crate::settings;
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use alloc::boxed::Box;
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use regalloc::{PrettyPrint, RealRegUniverse};
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use target_lexicon::{Architecture, ArmArchitecture, Triple};
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// New backend:
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mod abi;
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mod inst;
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mod lower;
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mod lower_inst;
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use inst::create_reg_universe;
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/// An ARM32 backend.
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pub struct Arm32Backend {
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triple: Triple,
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flags: settings::Flags,
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reg_universe: RealRegUniverse,
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}
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impl Arm32Backend {
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/// Create a new ARM32 backend with the given (shared) flags.
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pub fn new_with_flags(triple: Triple, flags: settings::Flags) -> Arm32Backend {
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let reg_universe = create_reg_universe();
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Arm32Backend {
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triple,
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flags,
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reg_universe,
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}
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}
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fn compile_vcode(
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&self,
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func: &Function,
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flags: settings::Flags,
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) -> CodegenResult<VCode<inst::Inst>> {
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// This performs lowering to VCode, register-allocates the code, computes
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// block layout and finalizes branches. The result is ready for binary emission.
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let abi = Box::new(abi::Arm32ABICallee::new(func, flags)?);
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compile::compile::<Arm32Backend>(func, self, abi)
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}
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}
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impl MachBackend for Arm32Backend {
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fn compile_function(
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&self,
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func: &Function,
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want_disasm: bool,
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) -> CodegenResult<MachCompileResult> {
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let flags = self.flags();
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let vcode = self.compile_vcode(func, flags.clone())?;
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let buffer = vcode.emit();
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let frame_size = vcode.frame_size();
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let disasm = if want_disasm {
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Some(vcode.show_rru(Some(&create_reg_universe())))
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} else {
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None
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};
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let buffer = buffer.finish();
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Ok(MachCompileResult {
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buffer,
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frame_size,
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disasm,
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})
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}
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fn name(&self) -> &'static str {
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"arm32"
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}
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fn triple(&self) -> Triple {
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self.triple.clone()
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}
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fn flags(&self) -> &settings::Flags {
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&self.flags
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}
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fn reg_universe(&self) -> &RealRegUniverse {
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&self.reg_universe
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}
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fn unsigned_add_overflow_condition(&self) -> IntCC {
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// Carry flag set.
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IntCC::UnsignedGreaterThanOrEqual
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}
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fn unsigned_sub_overflow_condition(&self) -> IntCC {
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// Carry flag clear.
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IntCC::UnsignedLessThan
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}
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}
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/// Create a new `isa::Builder`.
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pub fn isa_builder(triple: Triple) -> IsaBuilder {
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assert!(match triple.architecture {
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Architecture::Arm(ArmArchitecture::Arm)
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| Architecture::Arm(ArmArchitecture::Armv7)
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| Architecture::Arm(ArmArchitecture::Armv6) => true,
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_ => false,
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});
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IsaBuilder {
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triple,
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setup: settings::builder(),
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constructor: |triple, shared_flags, _| {
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let backend = Arm32Backend::new_with_flags(triple, shared_flags);
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Box::new(TargetIsaAdapter::new(backend))
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},
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}
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}
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