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712ff2249287ac5b7f828effc06c31ce22633957
wasmtime/cranelift/codegen/src/isa/aarch64/inst
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Chris Fallin 712ff22492 AArch64 SIMD: pattern-match load+splat into LD1R instruction.
2020-11-16 15:59:28 -08:00
..
unwind
machinst aarch64: New backend unwind (#2313)
2020-11-06 08:02:45 -06:00
args.rs
AArch64 SIMD: pattern-match load+splat into LD1R instruction.
2020-11-16 15:59:28 -08:00
emit_tests.rs
Cranelift AArch64: Various small fixes
2020-11-12 13:54:05 +00:00
emit.rs
Cranelift AArch64: Various small fixes
2020-11-12 13:54:05 +00:00
imms.rs
Cranelift AArch64: Improve code generation for vector constants
2020-10-30 13:16:12 +00:00
mod.rs
AArch64 SIMD: pattern-match load+splat into LD1R instruction.
2020-11-16 15:59:28 -08:00
regs.rs
Fix AArch64 ABI to respect half-caller-save, half-callee-save vec regs.
2020-10-06 14:44:02 -07:00
unwind.rs
aarch64/inst/unwind.rs: handle zero-length prologues correctly.
2020-11-12 17:41:21 +01:00
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