70cbc4ca7c
This refactors the handling of Inst::Extend and simplifies the lowering of Bextend and Bmask, which allows the use of SBFX instructions for extensions from 1-bit booleans. Other extensions use aliases of BFM, and the code was changed to reflect that, rather than hard coding bit patterns. Also ImmLogic is now implemented, so another hard coded instruction can be removed. As part of looking at boolean handling, `normalize_boolean_result` was changed to `materialize_boolean_result`, such that it can use either CSET or CSETM. Using CSETM saves an instruction (previously CSET + SUB) for booleans bigger than 1-bit. Copyright (c) 2020, Arm Limited.
37 lines
717 B
Plaintext
37 lines
717 B
Plaintext
test compile
|
|
target aarch64
|
|
|
|
function %uaddsat64(i64, i64) -> i64 {
|
|
block0(v0: i64, v1: i64):
|
|
v2 = uadd_sat.i64 v0, v1
|
|
return v2
|
|
}
|
|
|
|
; check: stp fp, lr, [sp, #-16]!
|
|
; nextln: mov fp, sp
|
|
; nextln: fmov d0, x0
|
|
; nextln: fmov d1, x1
|
|
; nextln: uqadd d0, d0, d1
|
|
; nextln: mov x0, v0.d[0]
|
|
; nextln: mov sp, fp
|
|
; nextln: ldp fp, lr, [sp], #16
|
|
; nextln: ret
|
|
|
|
function %uaddsat8(i8, i8) -> i8 {
|
|
block0(v0: i8, v1: i8):
|
|
v2 = uadd_sat.i8 v0, v1
|
|
return v2
|
|
}
|
|
|
|
; check: stp fp, lr, [sp, #-16]!
|
|
; nextln: mov fp, sp
|
|
; nextln: uxtb w0, w0
|
|
; nextln: uxtb w1, w1
|
|
; nextln: fmov d0, x0
|
|
; nextln: fmov d1, x1
|
|
; nextln: uqadd d0, d0, d1
|
|
; nextln: mov x0, v0.d[0]
|
|
; nextln: mov sp, fp
|
|
; nextln: ldp fp, lr, [sp], #16
|
|
; nextln: ret
|