7054f25abb
Adds support for transforming integer division and remainder by constants
into sequences that do not involve division instructions.
* div/rem by constant powers of two are turned into right shifts, plus some
fixups for the signed cases.
* div/rem by constant non-powers of two are turned into double length
multiplies by a magic constant, plus some fixups involving shifts,
addition and subtraction, that depends on the constant, the word size and
the signedness involved.
* The following cases are transformed: div and rem, signed or unsigned, 32
or 64 bit. The only un-transformed cases are: unsigned div and rem by
zero, signed div and rem by zero or -1.
* This is all incorporated within a new transformation pass, "preopt", in
lib/cretonne/src/preopt.rs.
* In preopt.rs, fn do_preopt() is the main driver. It is designed to be
extensible to transformations of other kinds of instructions. Currently
it merely uses a helper to identify div/rem transformation candidates and
another helper to perform the transformation.
* In preopt.rs, fn get_div_info() pattern matches to find candidates, both
cases where the second arg is an immediate, and cases where the second
arg is an identifier bound to an immediate at its definition point.
* In preopt.rs, fn do_divrem_transformation() does the heavy lifting of the
transformation proper. It in turn uses magic{S,U}{32,64} to calculate the
magic numbers required for the transformations.
* There are many test cases for the transformation proper:
filetests/preopt/div_by_const_non_power_of_2.cton
filetests/preopt/div_by_const_power_of_2.cton
filetests/preopt/rem_by_const_non_power_of_2.cton
filetests/preopt/rem_by_const_power_of_2.cton
filetests/preopt/div_by_const_indirect.cton
preopt.rs also contains a set of tests for magic number generation.
* The main (non-power-of-2) transformation requires instructions that return
the high word of a double-length multiply. For this, instructions umulhi
and smulhi have been added to the core instruction set. These will map
directly to single instructions on most non-intel targets.
* intel does not have an instruction exactly like that. For intel,
instructions x86_umulx and x86_smulx have been added. These map to real
instructions and return both result words. The intel legaliser will
rewrite {s,u}mulhi into x86_{s,u}mulx uses that throw away the lower half
word. Tests:
filetests/isa/intel/legalize-mulhi.cton (new file)
filetests/isa/intel/binary64.cton (added x86_{s,u}mulx encoding tests)
174 lines
5.3 KiB
Python
174 lines
5.3 KiB
Python
"""
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Supplementary instruction definitions for Intel.
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This module defines additional instructions that are useful only to the Intel
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target ISA.
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"""
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from base.types import iflags
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from cdsl.operands import Operand
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from cdsl.typevar import TypeVar
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from cdsl.instructions import Instruction, InstructionGroup
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GROUP = InstructionGroup("x86", "Intel-specific instruction set")
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iWord = TypeVar('iWord', 'A scalar integer machine word', ints=(32, 64))
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nlo = Operand('nlo', iWord, doc='Low part of numerator')
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nhi = Operand('nhi', iWord, doc='High part of numerator')
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d = Operand('d', iWord, doc='Denominator')
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q = Operand('q', iWord, doc='Quotient')
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r = Operand('r', iWord, doc='Remainder')
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udivmodx = Instruction(
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'x86_udivmodx', r"""
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Extended unsigned division.
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Concatenate the bits in `nhi` and `nlo` to form the numerator.
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Interpret the bits as an unsigned number and divide by the unsigned
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denominator `d`. Trap when `d` is zero or if the quotient is larger
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than the range of the output.
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Return both quotient and remainder.
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""",
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ins=(nlo, nhi, d), outs=(q, r), can_trap=True)
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sdivmodx = Instruction(
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'x86_sdivmodx', r"""
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Extended signed division.
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Concatenate the bits in `nhi` and `nlo` to form the numerator.
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Interpret the bits as a signed number and divide by the signed
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denominator `d`. Trap when `d` is zero or if the quotient is outside
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the range of the output.
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Return both quotient and remainder.
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""",
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ins=(nlo, nhi, d), outs=(q, r), can_trap=True)
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argL = Operand('argL', iWord)
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argR = Operand('argR', iWord)
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resLo = Operand('resLo', iWord)
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resHi = Operand('resHi', iWord)
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umulx = Instruction(
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'x86_umulx', r"""
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Unsigned integer multiplication, producing a double-length result.
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Polymorphic over all scalar integer types, but does not support vector
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types.
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""",
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ins=(argL, argR), outs=(resLo, resHi))
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smulx = Instruction(
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'x86_smulx', r"""
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Signed integer multiplication, producing a double-length result.
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Polymorphic over all scalar integer types, but does not support vector
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types.
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""",
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ins=(argL, argR), outs=(resLo, resHi))
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Float = TypeVar(
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'Float', 'A scalar or vector floating point number',
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floats=True, simd=True)
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IntTo = TypeVar(
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'IntTo', 'An integer type with the same number of lanes',
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ints=(32, 64), simd=True)
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x = Operand('x', Float)
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a = Operand('a', IntTo)
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cvtt2si = Instruction(
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'x86_cvtt2si', r"""
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Convert with truncation floating point to signed integer.
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The source floating point operand is converted to a signed integer by
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rounding towards zero. If the result can't be represented in the output
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type, returns the smallest signed value the output type can represent.
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This instruction does not trap.
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""",
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ins=x, outs=a)
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x = Operand('x', Float)
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a = Operand('a', Float)
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y = Operand('y', Float)
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fmin = Instruction(
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'x86_fmin', r"""
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Floating point minimum with Intel semantics.
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This is equivalent to the C ternary operator `x < y ? x : y` which
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differs from :inst:`fmin` when either operand is NaN or when comparing
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+0.0 to -0.0.
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When the two operands don't compare as LT, `y` is returned unchanged,
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even if it is a signalling NaN.
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""",
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ins=(x, y), outs=a)
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fmax = Instruction(
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'x86_fmax', r"""
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Floating point maximum with Intel semantics.
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This is equivalent to the C ternary operator `x > y ? x : y` which
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differs from :inst:`fmax` when either operand is NaN or when comparing
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+0.0 to -0.0.
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When the two operands don't compare as GT, `y` is returned unchanged,
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even if it is a signalling NaN.
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""",
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ins=(x, y), outs=a)
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x = Operand('x', iWord)
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push = Instruction(
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'x86_push', r"""
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Pushes a value onto the stack.
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Decrements the stack pointer and stores the specified value on to the top.
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This is polymorphic in i32 and i64. However, it is only implemented for i64
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in 64-bit mode, and only for i32 in 32-bit mode.
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""",
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ins=x, can_store=True, other_side_effects=True)
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pop = Instruction(
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'x86_pop', r"""
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Pops a value from the stack.
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Loads a value from the top of the stack and then increments the stack
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pointer.
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This is polymorphic in i32 and i64. However, it is only implemented for i64
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in 64-bit mode, and only for i32 in 32-bit mode.
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""",
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outs=x, can_load=True, other_side_effects=True)
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y = Operand('y', iWord)
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rflags = Operand('rflags', iflags)
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bsr = Instruction(
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'x86_bsr', r"""
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Bit Scan Reverse -- returns the bit-index of the most significant 1
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in the word. Result is undefined if the argument is zero. However, it
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sets the Z flag depending on the argument, so it is at least easy to
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detect and handle that case.
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This is polymorphic in i32 and i64. It is implemented for both i64 and
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i32 in 64-bit mode, and only for i32 in 32-bit mode.
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""",
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ins=x, outs=(y, rflags))
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bsf = Instruction(
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'x86_bsf', r"""
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Bit Scan Forwards -- returns the bit-index of the least significant 1
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in the word. Is otherwise identical to 'bsr', just above.
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""",
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ins=x, outs=(y, rflags))
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GROUP.close()
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