6fd0451bc3
This exposes the functionality of `fde::map_reg` on the `TargetIsa` trait, avoiding compilation errors on architectures where register mapping is not yet supported. The change is conditially compiled under the `unwind` feature.
442 lines
14 KiB
Rust
442 lines
14 KiB
Rust
//! Support for FDE data generation.
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use crate::binemit::{FrameUnwindOffset, FrameUnwindSink, Reloc};
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use crate::ir::{FrameLayoutChange, Function};
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use crate::isa::fde::RegisterMappingError;
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use crate::isa::{CallConv, RegUnit, TargetIsa};
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use alloc::vec::Vec;
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use core::convert::TryInto;
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use gimli::write::{
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Address, CallFrameInstruction, CommonInformationEntry, EhFrame, EndianVec,
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FrameDescriptionEntry, FrameTable, Result, Writer,
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};
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use gimli::{Encoding, Format, LittleEndian, Register, X86_64};
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pub type FDERelocEntry = (FrameUnwindOffset, Reloc);
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const FUNCTION_ENTRY_ADDRESS: Address = Address::Symbol {
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symbol: 0,
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addend: 0,
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};
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#[derive(Clone)]
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struct FDEWriter {
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vec: EndianVec<LittleEndian>,
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relocs: Vec<FDERelocEntry>,
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}
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impl FDEWriter {
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fn new() -> Self {
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Self {
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vec: EndianVec::new(LittleEndian),
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relocs: Vec::new(),
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}
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}
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fn into_vec_and_relocs(self) -> (Vec<u8>, Vec<FDERelocEntry>) {
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(self.vec.into_vec(), self.relocs)
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}
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}
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impl Writer for FDEWriter {
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type Endian = LittleEndian;
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fn endian(&self) -> Self::Endian {
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LittleEndian
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}
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fn len(&self) -> usize {
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self.vec.len()
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}
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fn write(&mut self, bytes: &[u8]) -> Result<()> {
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self.vec.write(bytes)
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}
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fn write_at(&mut self, offset: usize, bytes: &[u8]) -> Result<()> {
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self.vec.write_at(offset, bytes)
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}
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fn write_address(&mut self, address: Address, size: u8) -> Result<()> {
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match address {
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Address::Constant(_) => self.vec.write_address(address, size),
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Address::Symbol { .. } => {
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assert_eq!(address, FUNCTION_ENTRY_ADDRESS);
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let rt = match size {
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4 => Reloc::Abs4,
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8 => Reloc::Abs8,
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_ => {
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panic!("Unexpected address size at FDEWriter::write_address");
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}
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};
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self.relocs.push((self.vec.len().try_into().unwrap(), rt));
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self.vec.write_udata(0, size)
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}
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}
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}
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}
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fn return_address_reg(isa: &dyn TargetIsa) -> Register {
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assert!(isa.name() == "x86" && isa.pointer_bits() == 64);
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X86_64::RA
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}
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/// Map Cranelift registers to their corresponding Gimli registers.
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pub fn map_reg(
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isa: &dyn TargetIsa,
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reg: RegUnit,
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) -> core::result::Result<Register, RegisterMappingError> {
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if isa.name() != "x86" || isa.pointer_bits() != 64 {
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return Err(RegisterMappingError::UnsupportedArchitecture);
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}
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// Mapping from https://github.com/bytecodealliance/cranelift/pull/902 by @iximeow
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const X86_GP_REG_MAP: [gimli::Register; 16] = [
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X86_64::RAX,
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X86_64::RCX,
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X86_64::RDX,
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X86_64::RBX,
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X86_64::RSP,
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X86_64::RBP,
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X86_64::RSI,
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X86_64::RDI,
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X86_64::R8,
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X86_64::R9,
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X86_64::R10,
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X86_64::R11,
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X86_64::R12,
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X86_64::R13,
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X86_64::R14,
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X86_64::R15,
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];
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const X86_XMM_REG_MAP: [gimli::Register; 16] = [
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X86_64::XMM0,
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X86_64::XMM1,
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X86_64::XMM2,
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X86_64::XMM3,
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X86_64::XMM4,
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X86_64::XMM5,
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X86_64::XMM6,
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X86_64::XMM7,
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X86_64::XMM8,
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X86_64::XMM9,
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X86_64::XMM10,
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X86_64::XMM11,
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X86_64::XMM12,
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X86_64::XMM13,
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X86_64::XMM14,
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X86_64::XMM15,
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];
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let reg_info = isa.register_info();
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let bank = reg_info
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.bank_containing_regunit(reg)
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.ok_or_else(|| RegisterMappingError::MissingBank)?;
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match bank.name {
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"IntRegs" => {
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// x86 GP registers have a weird mapping to DWARF registers, so we use a
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// lookup table.
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Ok(X86_GP_REG_MAP[(reg - bank.first_unit) as usize])
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}
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"FloatRegs" => Ok(X86_XMM_REG_MAP[(reg - bank.first_unit) as usize]),
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_ => Err(RegisterMappingError::UnsupportedRegisterBank(bank.name)),
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}
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}
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fn to_cfi(
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isa: &dyn TargetIsa,
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change: &FrameLayoutChange,
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cfa_def_reg: &mut Register,
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cfa_def_offset: &mut i32,
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) -> Option<CallFrameInstruction> {
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Some(match change {
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FrameLayoutChange::CallFrameAddressAt { reg, offset } => {
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let mapped = map_reg(isa, *reg).expect("a register mapping from cranelift to gimli");
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let offset = (*offset) as i32;
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if mapped != *cfa_def_reg && offset != *cfa_def_offset {
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*cfa_def_reg = mapped;
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*cfa_def_offset = offset;
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CallFrameInstruction::Cfa(mapped, offset)
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} else if offset != *cfa_def_offset {
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*cfa_def_offset = offset;
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CallFrameInstruction::CfaOffset(offset)
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} else if mapped != *cfa_def_reg {
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*cfa_def_reg = mapped;
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CallFrameInstruction::CfaRegister(mapped)
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} else {
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return None;
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}
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}
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FrameLayoutChange::RegAt { reg, cfa_offset } => {
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assert!(cfa_offset % -8 == 0);
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let cfa_offset = *cfa_offset as i32;
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let mapped = map_reg(isa, *reg).expect("a register mapping from cranelift to gimli");
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CallFrameInstruction::Offset(mapped, cfa_offset)
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}
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FrameLayoutChange::ReturnAddressAt { cfa_offset } => {
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assert!(cfa_offset % -8 == 0);
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let cfa_offset = *cfa_offset as i32;
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CallFrameInstruction::Offset(X86_64::RA, cfa_offset)
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}
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FrameLayoutChange::Preserve => CallFrameInstruction::RememberState,
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FrameLayoutChange::Restore => CallFrameInstruction::RestoreState,
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})
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}
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/// Creates FDE structure from FrameLayout.
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pub fn emit_fde(func: &Function, isa: &dyn TargetIsa, sink: &mut dyn FrameUnwindSink) {
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assert!(isa.name() == "x86");
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// Expecting function with System V prologue
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assert!(
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func.signature.call_conv == CallConv::Fast
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|| func.signature.call_conv == CallConv::Cold
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|| func.signature.call_conv == CallConv::SystemV
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);
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assert!(func.frame_layout.is_some(), "expected func.frame_layout");
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let frame_layout = func.frame_layout.as_ref().unwrap();
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let mut blocks = func.layout.blocks().collect::<Vec<_>>();
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blocks.sort_by_key(|block| func.offsets[*block]); // Ensure inst offsets always increase
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let encinfo = isa.encoding_info();
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let mut last_offset = 0;
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let mut changes = Vec::new();
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for block in blocks {
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for (offset, inst, size) in func.inst_offsets(block, &encinfo) {
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let address_offset = (offset + size) as usize;
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assert!(last_offset <= address_offset);
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if let Some(cmds) = frame_layout.instructions.get(&inst) {
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for cmd in cmds.iter() {
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changes.push((address_offset, *cmd));
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}
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}
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last_offset = address_offset;
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}
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}
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let len = last_offset as u32;
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let word_size = isa.pointer_bytes() as i32;
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let encoding = Encoding {
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format: Format::Dwarf32,
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version: 1,
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address_size: word_size as u8,
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};
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let mut frames = FrameTable::default();
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let mut cfa_def_reg = return_address_reg(isa);
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let mut cfa_def_offset = 0i32;
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let mut cie = CommonInformationEntry::new(
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encoding,
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/* code_alignment_factor = */ 1,
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/* data_alignment_factor = */ -word_size as i8,
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return_address_reg(isa),
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);
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for ch in frame_layout.initial.iter() {
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if let Some(cfi) = to_cfi(isa, ch, &mut cfa_def_reg, &mut cfa_def_offset) {
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cie.add_instruction(cfi);
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}
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}
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let cie_id = frames.add_cie(cie);
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let mut fde = FrameDescriptionEntry::new(FUNCTION_ENTRY_ADDRESS, len);
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for (addr, ch) in changes.iter() {
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if let Some(cfi) = to_cfi(isa, ch, &mut cfa_def_reg, &mut cfa_def_offset) {
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fde.add_instruction((*addr) as u32, cfi);
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}
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}
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frames.add_fde(cie_id, fde);
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let mut eh_frame = EhFrame::from(FDEWriter::new());
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frames.write_eh_frame(&mut eh_frame).unwrap();
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let (bytes, relocs) = eh_frame.clone().into_vec_and_relocs();
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let unwind_start = sink.len();
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sink.bytes(&bytes);
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for (off, r) in relocs {
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sink.reloc(r, off + unwind_start);
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}
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let cie_len = u32::from_le_bytes(bytes.as_slice()[..4].try_into().unwrap());
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let fde_offset = cie_len as usize + 4;
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sink.set_entry_offset(unwind_start + fde_offset);
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// Need 0 marker for GCC unwind to end FDE "list".
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sink.bytes(&[0, 0, 0, 0]);
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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use crate::binemit::{FrameUnwindOffset, Reloc};
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use crate::cursor::{Cursor, FuncCursor};
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use crate::ir::{
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types, AbiParam, ExternalName, InstBuilder, Signature, StackSlotData, StackSlotKind,
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TrapCode,
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};
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use crate::isa::{lookup, CallConv};
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use crate::settings::{builder, Flags};
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use crate::Context;
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use std::str::FromStr;
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use target_lexicon::triple;
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struct SimpleUnwindSink(pub Vec<u8>, pub usize, pub Vec<(Reloc, usize)>);
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impl FrameUnwindSink for SimpleUnwindSink {
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fn len(&self) -> FrameUnwindOffset {
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self.0.len()
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}
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fn bytes(&mut self, b: &[u8]) {
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self.0.extend_from_slice(b);
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}
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fn reloc(&mut self, r: Reloc, off: FrameUnwindOffset) {
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self.2.push((r, off));
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}
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fn set_entry_offset(&mut self, off: FrameUnwindOffset) {
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self.1 = off;
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}
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}
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#[test]
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fn test_simple_func() {
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let isa = lookup(triple!("x86_64"))
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.expect("expect x86 ISA")
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.finish(Flags::new(builder()));
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let mut context = Context::for_function(create_function(
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CallConv::SystemV,
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Some(StackSlotData::new(StackSlotKind::ExplicitSlot, 64)),
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));
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context.func.collect_frame_layout_info();
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context.compile(&*isa).expect("expected compilation");
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let mut sink = SimpleUnwindSink(Vec::new(), 0, Vec::new());
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emit_fde(&context.func, &*isa, &mut sink);
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assert_eq!(
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sink.0,
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vec![
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20, 0, 0, 0, // CIE len
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0, 0, 0, 0, // CIE marker
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1, // version
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0, // augmentation string
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1, // code aligment = 1
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120, // data alignment = -8
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16, // RA = r16
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0x0c, 0x07, 0x08, // DW_CFA_def_cfa r7, 8
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0x90, 0x01, // DW_CFA_offset r16, -8 * 1
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0, 0, 0, 0, 0, 0, // padding
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36, 0, 0, 0, // FDE len
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28, 0, 0, 0, // CIE offset
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0, 0, 0, 0, 0, 0, 0, 0, // addr reloc
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16, 0, 0, 0, 0, 0, 0, 0, // function length
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0x42, // DW_CFA_advance_loc 2
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0x0e, 0x10, // DW_CFA_def_cfa_offset 16
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0x86, 0x02, // DW_CFA_offset r6, -8 * 2
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0x43, // DW_CFA_advance_loc 3
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0x0d, 0x06, // DW_CFA_def_cfa_register
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0x4a, // DW_CFA_advance_loc 10
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0x0c, 0x07, 0x08, // DW_CFA_def_cfa r7, 8
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0, 0, 0, 0, // padding
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0, 0, 0, 0, // End of FDEs
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]
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);
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assert_eq!(sink.1, 24);
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assert_eq!(sink.2.len(), 1);
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}
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fn create_function(call_conv: CallConv, stack_slot: Option<StackSlotData>) -> Function {
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let mut func =
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Function::with_name_signature(ExternalName::user(0, 0), Signature::new(call_conv));
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let block0 = func.dfg.make_block();
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let mut pos = FuncCursor::new(&mut func);
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pos.insert_block(block0);
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pos.ins().return_(&[]);
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if let Some(stack_slot) = stack_slot {
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func.stack_slots.push(stack_slot);
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}
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func
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}
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#[test]
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fn test_multi_return_func() {
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let isa = lookup(triple!("x86_64"))
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.expect("expect x86 ISA")
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.finish(Flags::new(builder()));
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let mut context = Context::for_function(create_multi_return_function(CallConv::SystemV));
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context.func.collect_frame_layout_info();
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context.compile(&*isa).expect("expected compilation");
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let mut sink = SimpleUnwindSink(Vec::new(), 0, Vec::new());
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emit_fde(&context.func, &*isa, &mut sink);
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assert_eq!(
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sink.0,
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vec![
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20, 0, 0, 0, // CIE len
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0, 0, 0, 0, // CIE marker
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1, // version
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0, // augmentation string
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1, // code aligment = 1
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120, // data alignment = -8
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16, // RA = r16
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0x0c, 0x07, 0x08, // DW_CFA_def_cfa r7, 8
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0x90, 0x01, // DW_CFA_offset r16, -8 * 1
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0, 0, 0, 0, 0, 0, // padding
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36, 0, 0, 0, // FDE len
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28, 0, 0, 0, // CIE offset
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0, 0, 0, 0, 0, 0, 0, 0, // addr reloc
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15, 0, 0, 0, 0, 0, 0, 0, // function length
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0x42, // DW_CFA_advance_loc 2
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0x0e, 0x10, // DW_CFA_def_cfa_offset 16
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0x86, 0x02, // DW_CFA_offset r6, -8 * 2
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0x43, // DW_CFA_advance_loc 3
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0x0d, 0x06, // DW_CFA_def_cfa_register
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0x47, // DW_CFA_advance_loc 10
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0x0a, // DW_CFA_preserve_state
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0x0c, 0x07, 0x08, // DW_CFA_def_cfa r7, 8
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0x41, // DW_CFA_advance_loc 1
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0x0b, // DW_CFA_restore_state
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// NOTE: no additional CFA directives -- DW_CFA_restore_state
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// is done before trap and it is last instruction in the function.
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0, // padding
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0, 0, 0, 0, // End of FDEs
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]
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);
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assert_eq!(sink.1, 24);
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assert_eq!(sink.2.len(), 1);
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}
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fn create_multi_return_function(call_conv: CallConv) -> Function {
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let mut sig = Signature::new(call_conv);
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sig.params.push(AbiParam::new(types::I32));
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let mut func = Function::with_name_signature(ExternalName::user(0, 0), sig);
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let block0 = func.dfg.make_block();
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let v0 = func.dfg.append_block_param(block0, types::I32);
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let block1 = func.dfg.make_block();
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let block2 = func.dfg.make_block();
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let mut pos = FuncCursor::new(&mut func);
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pos.insert_block(block0);
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pos.ins().brnz(v0, block2, &[]);
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pos.ins().jump(block1, &[]);
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pos.insert_block(block1);
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pos.ins().return_(&[]);
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pos.insert_block(block2);
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pos.ins().trap(TrapCode::User(0));
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func
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}
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}
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