6f66abd5c7
Following up on the discussion in https://github.com/bytecodealliance/wasmtime/pull/6011 this adds an improved implementation of TrapIf for s390x using a single conditional branch instruction. If the trap conditions is true, we branch into the middle of the branch instruction - those middle two bytes are zero, which matches the encoding of the trap instruction. In addition, show the trap code for Trap and TrapIf instructions in assembler output.
396 lines
7.8 KiB
Plaintext
396 lines
7.8 KiB
Plaintext
test compile precise-output
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target s390x
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; CALL
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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function %call(i64) -> i64 {
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fn0 = %g(i64) -> i64
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block0(v0: i64):
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v1 = call fn0(v0)
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return v1
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}
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; VCode:
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; stmg %r14, %r15, 112(%r15)
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; aghi %r15, -160
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; virtual_sp_offset_adjust 160
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; block0:
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; bras %r1, 12 ; data %g + 0 ; lg %r5, 0(%r1)
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; basr %r14, %r5
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; lmg %r14, %r15, 272(%r15)
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; br %r14
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;
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; Disassembled:
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; block0: ; offset 0x0
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; stmg %r14, %r15, 0x70(%r15)
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; aghi %r15, -0xa0
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; block1: ; offset 0xa
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; bras %r1, 0x16
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; .byte 0x00, 0x00 ; reloc_external Abs8 %g 0
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; .byte 0x00, 0x00
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; .byte 0x00, 0x00
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; .byte 0x00, 0x00
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; lg %r5, 0(%r1)
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; basr %r14, %r5
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; lmg %r14, %r15, 0x110(%r15)
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; br %r14
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function %call_uext(i32) -> i64 {
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fn0 = %g(i32 uext) -> i64
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block0(v0: i32):
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v1 = call fn0(v0)
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return v1
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}
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; VCode:
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; stmg %r14, %r15, 112(%r15)
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; aghi %r15, -160
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; virtual_sp_offset_adjust 160
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; block0:
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; llgfr %r2, %r2
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; bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1)
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; basr %r14, %r3
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; lmg %r14, %r15, 272(%r15)
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; br %r14
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;
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; Disassembled:
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; block0: ; offset 0x0
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; stmg %r14, %r15, 0x70(%r15)
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; aghi %r15, -0xa0
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; block1: ; offset 0xa
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; llgfr %r2, %r2
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; bras %r1, 0x1a
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; .byte 0x00, 0x00 ; reloc_external Abs8 %g 0
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; .byte 0x00, 0x00
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; .byte 0x00, 0x00
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; .byte 0x00, 0x00
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; lg %r3, 0(%r1)
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; basr %r14, %r3
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; lmg %r14, %r15, 0x110(%r15)
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; br %r14
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function %ret_uext(i32) -> i32 uext {
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block0(v0: i32):
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return v0
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}
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; VCode:
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; block0:
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; llgfr %r2, %r2
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; br %r14
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;
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; Disassembled:
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; block0: ; offset 0x0
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; llgfr %r2, %r2
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; br %r14
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function %call_uext(i32) -> i64 {
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fn0 = %g(i32 sext) -> i64
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block0(v0: i32):
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v1 = call fn0(v0)
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return v1
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}
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; VCode:
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; stmg %r14, %r15, 112(%r15)
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; aghi %r15, -160
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; virtual_sp_offset_adjust 160
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; block0:
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; lgfr %r2, %r2
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; bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1)
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; basr %r14, %r3
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; lmg %r14, %r15, 272(%r15)
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; br %r14
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;
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; Disassembled:
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; block0: ; offset 0x0
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; stmg %r14, %r15, 0x70(%r15)
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; aghi %r15, -0xa0
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; block1: ; offset 0xa
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; lgfr %r2, %r2
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; bras %r1, 0x1a
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; .byte 0x00, 0x00 ; reloc_external Abs8 %g 0
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; .byte 0x00, 0x00
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; .byte 0x00, 0x00
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; .byte 0x00, 0x00
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; lg %r3, 0(%r1)
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; basr %r14, %r3
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; lmg %r14, %r15, 0x110(%r15)
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; br %r14
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function %ret_uext(i32) -> i32 sext {
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block0(v0: i32):
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return v0
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}
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; VCode:
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; block0:
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; lgfr %r2, %r2
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; br %r14
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;
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; Disassembled:
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; block0: ; offset 0x0
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; lgfr %r2, %r2
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; br %r14
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function %call_colocated(i64) -> i64 {
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fn0 = colocated %g(i64) -> i64
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block0(v0: i64):
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v1 = call fn0(v0)
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return v1
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}
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; VCode:
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; stmg %r14, %r15, 112(%r15)
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; aghi %r15, -160
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; virtual_sp_offset_adjust 160
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; block0:
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; brasl %r14, %g
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; lmg %r14, %r15, 272(%r15)
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; br %r14
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;
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; Disassembled:
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; block0: ; offset 0x0
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; stmg %r14, %r15, 0x70(%r15)
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; aghi %r15, -0xa0
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; block1: ; offset 0xa
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; brasl %r14, 0xa ; reloc_external PLTRel32Dbl %g 2
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; lmg %r14, %r15, 0x110(%r15)
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; br %r14
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function %f2(i32) -> i64 {
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fn0 = %g(i32 uext) -> i64
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block0(v0: i32):
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v1 = call fn0(v0)
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return v1
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}
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; VCode:
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; stmg %r14, %r15, 112(%r15)
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; aghi %r15, -160
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; virtual_sp_offset_adjust 160
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; block0:
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; llgfr %r2, %r2
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; bras %r1, 12 ; data %g + 0 ; lg %r3, 0(%r1)
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; basr %r14, %r3
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; lmg %r14, %r15, 272(%r15)
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; br %r14
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;
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; Disassembled:
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; block0: ; offset 0x0
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; stmg %r14, %r15, 0x70(%r15)
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; aghi %r15, -0xa0
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; block1: ; offset 0xa
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; llgfr %r2, %r2
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; bras %r1, 0x1a
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; .byte 0x00, 0x00 ; reloc_external Abs8 %g 0
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; .byte 0x00, 0x00
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; .byte 0x00, 0x00
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; .byte 0x00, 0x00
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; lg %r3, 0(%r1)
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; basr %r14, %r3
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; lmg %r14, %r15, 0x110(%r15)
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; br %r14
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function %call_indirect(i64, i64) -> i64 {
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sig0 = (i64) -> i64
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block0(v0: i64, v1: i64):
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v2 = call_indirect.i64 sig0, v1(v0)
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return v2
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}
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; VCode:
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; stmg %r14, %r15, 112(%r15)
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; aghi %r15, -160
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; virtual_sp_offset_adjust 160
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; block0:
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; basr %r14, %r3
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; lmg %r14, %r15, 272(%r15)
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; br %r14
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;
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; Disassembled:
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; block0: ; offset 0x0
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; stmg %r14, %r15, 0x70(%r15)
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; aghi %r15, -0xa0
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; block1: ; offset 0xa
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; basr %r14, %r3
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; lmg %r14, %r15, 0x110(%r15)
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; br %r14
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function %incoming_args(i64, i32, i32 uext, i32 sext, i16, i16 uext, i16 sext, i8, i8 uext, i8 sext) -> i64 {
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block0(v0: i64, v1: i32, v2: i32, v3: i32, v4: i16, v5: i16, v6: i16, v7: i8, v8: i8, v9: i8):
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v10 = uextend.i64 v1
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v11 = uextend.i64 v2
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v12 = uextend.i64 v3
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v13 = uextend.i64 v4
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v14 = uextend.i64 v5
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v15 = uextend.i64 v6
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v16 = uextend.i64 v7
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v17 = uextend.i64 v8
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v18 = uextend.i64 v9
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v19 = iadd v0, v10
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v20 = iadd v11, v12
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v21 = iadd v13, v14
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v22 = iadd v15, v16
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v23 = iadd v17, v18
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v24 = iadd v19, v20
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v25 = iadd v21, v22
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v26 = iadd v23, v24
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v27 = iadd v25, v26
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return v27
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}
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; VCode:
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; stmg %r6, %r15, 48(%r15)
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; block0:
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; lg %r12, 160(%r15)
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; lg %r14, 168(%r15)
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; llgc %r7, 183(%r15)
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; lg %r9, 184(%r15)
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; lg %r11, 192(%r15)
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; llgfr %r3, %r3
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; llgfr %r4, %r4
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; llgfr %r13, %r5
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; llghr %r6, %r6
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; llghr %r5, %r12
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; llghr %r12, %r14
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; llgcr %r14, %r7
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; llgcr %r7, %r9
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; llgcr %r8, %r11
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; agrk %r3, %r2, %r3
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; agr %r4, %r13
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; agrk %r5, %r6, %r5
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; agrk %r2, %r12, %r14
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; agrk %r12, %r7, %r8
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; agr %r3, %r4
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; agrk %r4, %r5, %r2
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; agrk %r3, %r12, %r3
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; agrk %r2, %r4, %r3
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; lmg %r6, %r15, 48(%r15)
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; br %r14
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;
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; Disassembled:
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; block0: ; offset 0x0
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; stmg %r6, %r15, 0x30(%r15)
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; block1: ; offset 0x6
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; lg %r12, 0xa0(%r15)
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; lg %r14, 0xa8(%r15)
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; llgc %r7, 0xb7(%r15)
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; lg %r9, 0xb8(%r15)
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; lg %r11, 0xc0(%r15)
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; llgfr %r3, %r3
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; llgfr %r4, %r4
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; llgfr %r13, %r5
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; llghr %r6, %r6
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; llghr %r5, %r12
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; llghr %r12, %r14
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; llgcr %r14, %r7
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; llgcr %r7, %r9
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; llgcr %r8, %r11
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; agrk %r3, %r2, %r3
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; agr %r4, %r13
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; agrk %r5, %r6, %r5
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; agrk %r2, %r12, %r14
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; agrk %r12, %r7, %r8
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; agr %r3, %r4
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; agrk %r4, %r5, %r2
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; agrk %r3, %r12, %r3
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; agrk %r2, %r4, %r3
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; lmg %r6, %r15, 0x30(%r15)
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; br %r14
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function %incoming_args_i128(i128, i128, i128, i128, i128, i128, i128, i128) -> i128 {
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block0(v0: i128, v1: i128, v2: i128, v3: i128, v4: i128, v5: i128, v6: i128, v7: i128):
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v8 = iadd v0, v1
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v9 = iadd v2, v3
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v10 = iadd v4, v5
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v11 = iadd v6, v7
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v12 = iadd v8, v9
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v13 = iadd v10, v11
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v14 = iadd v12, v13
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return v14
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}
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; VCode:
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; block0:
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; vl %v1, 0(%r3)
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; vl %v3, 0(%r4)
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; vl %v5, 0(%r5)
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; vl %v7, 0(%r6)
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; lg %r3, 160(%r15)
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; vl %v18, 0(%r3)
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; lg %r3, 168(%r15)
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; vl %v21, 0(%r3)
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; lg %r5, 176(%r15)
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; vl %v24, 0(%r5)
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; lg %r4, 184(%r15)
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; vl %v27, 0(%r4)
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; vaq %v16, %v1, %v3
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; vaq %v17, %v5, %v7
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; vaq %v18, %v18, %v21
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; vaq %v19, %v24, %v27
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; vaq %v16, %v16, %v17
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; vaq %v17, %v18, %v19
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; vaq %v16, %v16, %v17
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; vst %v16, 0(%r2)
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; br %r14
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;
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; Disassembled:
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; block0: ; offset 0x0
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; vl %v1, 0(%r3)
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; vl %v3, 0(%r4)
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; vl %v5, 0(%r5)
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; vl %v7, 0(%r6)
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; lg %r3, 0xa0(%r15)
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; vl %v18, 0(%r3)
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; lg %r3, 0xa8(%r15)
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; vl %v21, 0(%r3)
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; lg %r5, 0xb0(%r15)
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; vl %v24, 0(%r5)
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; lg %r4, 0xb8(%r15)
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; vl %v27, 0(%r4)
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; vaq %v16, %v1, %v3
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; vaq %v17, %v5, %v7
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; vaq %v18, %v18, %v21
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; vaq %v19, %v24, %v27
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; vaq %v16, %v16, %v17
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; vaq %v17, %v18, %v19
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; vaq %v16, %v16, %v17
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; vst %v16, 0(%r2)
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; br %r14
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function %call_sret() -> i64 {
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fn0 = colocated %g(i64 sret)
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block0:
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v1 = iconst.i64 0
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call fn0(v1)
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trap user0
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}
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; VCode:
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; stmg %r14, %r15, 112(%r15)
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; aghi %r15, -160
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; virtual_sp_offset_adjust 160
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; block0:
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; lghi %r2, 0
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; brasl %r14, %g
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; .word 0x0000 # trap=user0
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;
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; Disassembled:
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; block0: ; offset 0x0
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; stmg %r14, %r15, 0x70(%r15)
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; aghi %r15, -0xa0
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; block1: ; offset 0xa
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; lghi %r2, 0
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; brasl %r14, 0xe ; reloc_external PLTRel32Dbl %g 2
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; .byte 0x00, 0x00 ; trap: user0
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