cb48ea406e
This PR switches the default backend on x86, for both the `cranelift-codegen` crate and for Wasmtime, to the new (`MachInst`-style, `VCode`-based) backend that has been under development and testing for some time now. The old backend is still available by default in builds with the `old-x86-backend` feature, or by requesting `BackendVariant::Legacy` from the appropriate APIs. As part of that switch, it adds some more runtime-configurable plumbing to the testing infrastructure so that tests can be run using the appropriate backend. `clif-util test` is now capable of parsing a backend selector option from filetests and instantiating the correct backend. CI has been updated so that the old x86 backend continues to run its tests, just as we used to run the new x64 backend separately. At some point, we will remove the old x86 backend entirely, once we are satisfied that the new backend has not caused any unforeseen issues and we do not need to revert.
72 lines
1.7 KiB
Plaintext
72 lines
1.7 KiB
Plaintext
test safepoint
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set enable_safepoints=true
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target x86_64 legacy
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function %test(i32, r64, r64) -> r64 {
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block0(v0: i32, v1:r64, v2:r64):
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jump block1(v0)
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block1(v3: i32):
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v4 = irsub_imm v3, 1
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jump block2(v4)
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block2(v5: i32):
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resumable_trap interrupt
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brz v5, block1(v5)
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jump block3
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block3:
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v6 = null.r64
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v7 = is_null v6
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brnz v7, block2(v0)
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jump block4
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block4:
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brnz v0, block5
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jump block6
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block5:
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return v1
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block6:
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return v2
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}
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; sameln: function %test(i32 [%rdi], r64 [%rsi], r64 [%rdx]) -> r64 [%rax] fast {
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; nextln: block0(v0: i32 [%rdi], v1: r64 [%rsi], v2: r64 [%rdx]):
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; nextln: v10 = copy v0
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; nextln: jump block1(v10)
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; nextln:
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; nextln: block7:
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; nextln: regmove.i32 v5, %rcx -> %rax
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; nextln: jump block1(v5)
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; nextln:
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; nextln: block1(v3: i32 [%rax]):
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; nextln: v8 = iconst.i32 1
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; nextln: v4 = isub v8, v3
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; nextln: jump block2(v4)
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; nextln:
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; nextln: block8:
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; nextln: v9 = copy.i32 v0
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; nextln: regmove v9, %rax -> %rcx
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; nextln: jump block2(v9)
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; nextln:
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; nextln: block2(v5: i32 [%rcx]):
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; nextln: safepoint v1, v2
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; nextln: resumable_trap interrupt
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; nextln: brz v5, block7
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; nextln: jump block3
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; nextln:
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; nextln: block3:
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; nextln: v6 = null.r64
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; nextln: v7 = is_null v6
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; nextln: brnz v7, block8
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; nextln: jump block4
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; nextln:
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; nextln: block4:
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; nextln: brnz.i32 v0, block5
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; nextln: jump block6
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; nextln:
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; nextln: block5:
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; nextln: regmove.r64 v1, %rsi -> %rax
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; nextln: return v1
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; nextln:
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; nextln: block6:
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; nextln: regmove.r64 v2, %rdx -> %rax
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; nextln: return v2
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; nextln: }
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