7248abd591
SIMD & FP registers are now saved and restored in pairs, similarly to general-purpose registers. Also, only the bottom 64 bits of the registers are saved and restored (in case of non-Baldrdash ABIs), which is the requirement from the Procedure Call Standard for the Arm 64-bit Architecture. As for the callee-saved general-purpose registers, if a procedure needs to save and restore an odd number of them, it no longer uses store and load pair instructions for the last register. Copyright (c) 2021, Arm Limited.
149 lines
3.4 KiB
Plaintext
149 lines
3.4 KiB
Plaintext
test compile
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set unwind_info=false
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target aarch64
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function %f(f64) -> f64 {
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block0(v0: f64):
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v1 = fadd.f64 v0, v0
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v2 = fadd.f64 v0, v0
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v3 = fadd.f64 v0, v0
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v4 = fadd.f64 v0, v0
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v5 = fadd.f64 v0, v0
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v6 = fadd.f64 v0, v0
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v7 = fadd.f64 v0, v0
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v8 = fadd.f64 v0, v0
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v9 = fadd.f64 v0, v0
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v10 = fadd.f64 v0, v0
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v11 = fadd.f64 v0, v0
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v12 = fadd.f64 v0, v0
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v13 = fadd.f64 v0, v0
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v14 = fadd.f64 v0, v0
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v15 = fadd.f64 v0, v0
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v16 = fadd.f64 v0, v0
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v17 = fadd.f64 v0, v0
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v18 = fadd.f64 v0, v0
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v19 = fadd.f64 v0, v0
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v20 = fadd.f64 v0, v0
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v21 = fadd.f64 v0, v0
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v22 = fadd.f64 v0, v0
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v23 = fadd.f64 v0, v0
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v24 = fadd.f64 v0, v0
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v25 = fadd.f64 v0, v0
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v26 = fadd.f64 v0, v0
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v27 = fadd.f64 v0, v0
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v28 = fadd.f64 v0, v0
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v29 = fadd.f64 v0, v0
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v30 = fadd.f64 v0, v0
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v31 = fadd.f64 v0, v0
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v32 = fadd.f64 v0, v1
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v33 = fadd.f64 v2, v3
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v34 = fadd.f64 v4, v5
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v35 = fadd.f64 v6, v7
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v36 = fadd.f64 v8, v9
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v37 = fadd.f64 v10, v11
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v38 = fadd.f64 v12, v13
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v39 = fadd.f64 v14, v15
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v40 = fadd.f64 v16, v17
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v41 = fadd.f64 v18, v19
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v42 = fadd.f64 v20, v21
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v43 = fadd.f64 v22, v23
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v44 = fadd.f64 v24, v25
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v45 = fadd.f64 v26, v27
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v46 = fadd.f64 v28, v29
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v47 = fadd.f64 v30, v31
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v48 = fadd.f64 v32, v33
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v49 = fadd.f64 v34, v35
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v50 = fadd.f64 v36, v37
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v51 = fadd.f64 v38, v39
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v52 = fadd.f64 v40, v41
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v53 = fadd.f64 v42, v43
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v54 = fadd.f64 v44, v45
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v55 = fadd.f64 v46, v47
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v56 = fadd.f64 v48, v49
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v57 = fadd.f64 v50, v51
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v58 = fadd.f64 v52, v53
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v59 = fadd.f64 v54, v55
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v60 = fadd.f64 v56, v57
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v61 = fadd.f64 v58, v59
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v62 = fadd.f64 v60, v61
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return v62
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: stp d14, d15, [sp, #-16]!
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; nextln: stp d12, d13, [sp, #-16]!
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; nextln: stp d10, d11, [sp, #-16]!
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; nextln: stp d8, d9, [sp, #-16]!
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; check: ldp d8, d9, [sp], #16
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; nextln: ldp d10, d11, [sp], #16
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; nextln: ldp d12, d13, [sp], #16
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; nextln: ldp d14, d15, [sp], #16
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f2(i64) -> i64 {
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block0(v0: i64):
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v1 = iadd.i64 v0, v0
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v2 = iadd.i64 v0, v1
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v3 = iadd.i64 v0, v2
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v4 = iadd.i64 v0, v3
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v5 = iadd.i64 v0, v4
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v6 = iadd.i64 v0, v5
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v7 = iadd.i64 v0, v6
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v8 = iadd.i64 v0, v7
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v9 = iadd.i64 v0, v8
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v10 = iadd.i64 v0, v9
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v11 = iadd.i64 v0, v10
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v12 = iadd.i64 v0, v11
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v13 = iadd.i64 v0, v12
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v14 = iadd.i64 v0, v13
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v15 = iadd.i64 v0, v14
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v16 = iadd.i64 v0, v15
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v17 = iadd.i64 v0, v16
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v18 = iadd.i64 v0, v17
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v19 = iadd.i64 v0, v1
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v20 = iadd.i64 v2, v3
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v21 = iadd.i64 v4, v5
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v22 = iadd.i64 v6, v7
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v23 = iadd.i64 v8, v9
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v24 = iadd.i64 v10, v11
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v25 = iadd.i64 v12, v13
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v26 = iadd.i64 v14, v15
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v27 = iadd.i64 v16, v17
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v28 = iadd.i64 v18, v19
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v29 = iadd.i64 v20, v21
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v30 = iadd.i64 v22, v23
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v31 = iadd.i64 v24, v25
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v32 = iadd.i64 v26, v27
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v33 = iadd.i64 v28, v29
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v34 = iadd.i64 v30, v31
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v35 = iadd.i64 v32, v33
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v36 = iadd.i64 v34, v35
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return v36
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: str x22, [sp, #-16]!
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; nextln: stp x19, x20, [sp, #-16]!
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; nextln: add x1, x0, x0
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; check: add x0, x1, x0
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; nextln: ldp x19, x20, [sp], #16
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; nextln: ldr x22, [sp], #16
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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