6da734221a
The encoding tables are keyed by the controlling type variable only. We need to distinguish different encodings for instructions with multiple type variables. Add a TypePredicate instruction predicate which can check the type of an instruction value operand. Combine type checks into the instruction predicate for instructions with more than one type variable. Add Intel encodings for fcvt_from_sint.f32.i64 which can now be distinguished from fcvt_from_sint.f32.i32.
140 lines
5.5 KiB
Plaintext
140 lines
5.5 KiB
Plaintext
; Binary emission of 64-bit floating point code.
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test binemit
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set is_64bit
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isa intel has_sse2
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; The binary encodings can be verified with the command:
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;
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; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary64-float.cton | llvm-mc -show-encoding -triple=x86_64
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;
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function %F32() {
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ebb0:
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[-,%r11] v0 = iconst.i32 1
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[-,%rsi] v1 = iconst.i32 2
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[-,%rax] v2 = iconst.i64 11
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[-,%r14] v3 = iconst.i64 12
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; asm: cvtsi2ssl %r11d, %xmm5
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[-,%xmm5] v10 = fcvt_from_sint.f32 v0 ; bin: f3 41 0f 2a eb
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; asm: cvtsi2ssl %esi, %xmm10
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[-,%xmm10] v11 = fcvt_from_sint.f32 v1 ; bin: f3 44 0f 2a d6
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; asm: cvtsi2ssq %rax, %xmm5
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[-,%xmm5] v12 = fcvt_from_sint.f32 v2 ; bin: f3 48 0f 2a e8
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; asm: cvtsi2ssq %r14, %xmm10
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[-,%xmm10] v13 = fcvt_from_sint.f32 v3 ; bin: f3 4d 0f 2a d6
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; Binary arithmetic.
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; asm: addss %xmm10, %xmm5
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[-,%xmm5] v20 = fadd v10, v11 ; bin: f3 41 0f 58 ea
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; asm: addss %xmm5, %xmm10
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[-,%xmm10] v21 = fadd v11, v10 ; bin: f3 44 0f 58 d5
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; asm: subss %xmm10, %xmm5
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[-,%xmm5] v22 = fsub v10, v11 ; bin: f3 41 0f 5c ea
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; asm: subss %xmm5, %xmm10
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[-,%xmm10] v23 = fsub v11, v10 ; bin: f3 44 0f 5c d5
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; asm: mulss %xmm10, %xmm5
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[-,%xmm5] v24 = fmul v10, v11 ; bin: f3 41 0f 59 ea
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; asm: mulss %xmm5, %xmm10
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[-,%xmm10] v25 = fmul v11, v10 ; bin: f3 44 0f 59 d5
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; asm: divss %xmm10, %xmm5
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[-,%xmm5] v26 = fdiv v10, v11 ; bin: f3 41 0f 5e ea
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; asm: divss %xmm5, %xmm10
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[-,%xmm10] v27 = fdiv v11, v10 ; bin: f3 44 0f 5e d5
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; Bitwise ops.
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; We use the *ps SSE instructions for everything because they are smaller.
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; asm: andps %xmm10, %xmm5
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[-,%xmm5] v30 = band v10, v11 ; bin: 41 0f 54 ea
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; asm: andps %xmm5, %xmm10
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[-,%xmm10] v31 = band v11, v10 ; bin: 44 0f 54 d5
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; asm: andnps %xmm10, %xmm5
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[-,%xmm5] v32 = band_not v10, v11 ; bin: 41 0f 55 ea
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; asm: andnps %xmm5, %xmm10
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[-,%xmm10] v33 = band_not v11, v10 ; bin: 44 0f 55 d5
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; asm: orps %xmm10, %xmm5
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[-,%xmm5] v34 = bor v10, v11 ; bin: 41 0f 56 ea
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; asm: orps %xmm5, %xmm10
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[-,%xmm10] v35 = bor v11, v10 ; bin: 44 0f 56 d5
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; asm: xorps %xmm10, %xmm5
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[-,%xmm5] v36 = bxor v10, v11 ; bin: 41 0f 57 ea
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; asm: xorps %xmm5, %xmm10
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[-,%xmm10] v37 = bxor v11, v10 ; bin: 44 0f 57 d5
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return
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}
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function %F64() {
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ebb0:
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[-,%r11] v0 = iconst.i32 1
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[-,%rsi] v1 = iconst.i32 2
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[-,%rax] v2 = iconst.i64 11
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[-,%r14] v3 = iconst.i64 12
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; asm: cvtsi2sdl %r11d, %xmm5
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[-,%xmm5] v10 = fcvt_from_sint.f64 v0 ; bin: f2 41 0f 2a eb
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; asm: cvtsi2sdl %esi, %xmm10
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[-,%xmm10] v11 = fcvt_from_sint.f64 v1 ; bin: f2 44 0f 2a d6
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; asm: cvtsi2sdq %rax, %xmm5
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[-,%xmm5] v12 = fcvt_from_sint.f64 v2 ; bin: f2 48 0f 2a e8
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; asm: cvtsi2sdq %r14, %xmm10
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[-,%xmm10] v13 = fcvt_from_sint.f64 v3 ; bin: f2 4d 0f 2a d6
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; Binary arithmetic.
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; asm: addsd %xmm10, %xmm5
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[-,%xmm5] v20 = fadd v10, v11 ; bin: f2 41 0f 58 ea
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; asm: addsd %xmm5, %xmm10
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[-,%xmm10] v21 = fadd v11, v10 ; bin: f2 44 0f 58 d5
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; asm: subsd %xmm10, %xmm5
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[-,%xmm5] v22 = fsub v10, v11 ; bin: f2 41 0f 5c ea
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; asm: subsd %xmm5, %xmm10
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[-,%xmm10] v23 = fsub v11, v10 ; bin: f2 44 0f 5c d5
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; asm: mulsd %xmm10, %xmm5
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[-,%xmm5] v24 = fmul v10, v11 ; bin: f2 41 0f 59 ea
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; asm: mulsd %xmm5, %xmm10
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[-,%xmm10] v25 = fmul v11, v10 ; bin: f2 44 0f 59 d5
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; asm: divsd %xmm10, %xmm5
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[-,%xmm5] v26 = fdiv v10, v11 ; bin: f2 41 0f 5e ea
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; asm: divsd %xmm5, %xmm10
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[-,%xmm10] v27 = fdiv v11, v10 ; bin: f2 44 0f 5e d5
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; Bitwise ops.
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; We use the *ps SSE instructions for everything because they are smaller.
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; asm: andps %xmm10, %xmm5
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[-,%xmm5] v30 = band v10, v11 ; bin: 41 0f 54 ea
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; asm: andps %xmm5, %xmm10
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[-,%xmm10] v31 = band v11, v10 ; bin: 44 0f 54 d5
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; asm: andnps %xmm10, %xmm5
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[-,%xmm5] v32 = band_not v10, v11 ; bin: 41 0f 55 ea
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; asm: andnps %xmm5, %xmm10
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[-,%xmm10] v33 = band_not v11, v10 ; bin: 44 0f 55 d5
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; asm: orps %xmm10, %xmm5
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[-,%xmm5] v34 = bor v10, v11 ; bin: 41 0f 56 ea
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; asm: orps %xmm5, %xmm10
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[-,%xmm10] v35 = bor v11, v10 ; bin: 44 0f 56 d5
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; asm: xorps %xmm10, %xmm5
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[-,%xmm5] v36 = bxor v10, v11 ; bin: 41 0f 57 ea
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; asm: xorps %xmm5, %xmm10
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[-,%xmm10] v37 = bxor v11, v10 ; bin: 44 0f 57 d5
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return
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}
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