During register allocation, the code must be kept in conventional SSA form. Add a verifier that checks this property.
123 lines
4.5 KiB
Rust
123 lines
4.5 KiB
Rust
//! Verify conventional SSA form.
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use dominator_tree::DominatorTree;
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use flowgraph::ControlFlowGraph;
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use ir::Function;
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use regalloc::liveness::Liveness;
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use regalloc::virtregs::VirtRegs;
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use std::cmp::Ordering;
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use verifier::Result;
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/// Verify conventional SSA form for `func`.
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///
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/// Conventional SSA form is represented in Cretonne with the help of virtual registers:
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///
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/// - Two values are said to be *PHI-related* if one is an EBB argument and the other is passed as
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/// a branch argument in a location that matches the first value.
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/// - PHI-related values must belong to the same virtual register.
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/// - Two values in the same virtual register must not have overlapping live ranges.
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///
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/// Additionally, we verify this property of virtual registers:
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///
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/// - The values in a virtual register are ordered according to the dominator tree's `rpo_cmp()`.
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///
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/// We don't verify that virtual registers are minimal. Minimal CSSA is not required.
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pub fn verify_cssa(func: &Function,
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cfg: &ControlFlowGraph,
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domtree: &DominatorTree,
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liveness: &Liveness,
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virtregs: &VirtRegs)
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-> Result {
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let verifier = CssaVerifier {
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func,
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cfg,
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domtree,
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virtregs,
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liveness,
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};
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verifier.check_virtregs()?;
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verifier.check_cssa()?;
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Ok(())
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}
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struct CssaVerifier<'a> {
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func: &'a Function,
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cfg: &'a ControlFlowGraph,
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domtree: &'a DominatorTree,
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virtregs: &'a VirtRegs,
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liveness: &'a Liveness,
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}
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impl<'a> CssaVerifier<'a> {
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fn check_virtregs(&self) -> Result {
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for vreg in self.virtregs.all_virtregs() {
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let values = self.virtregs.values(vreg);
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for (idx, &val) in values.iter().enumerate() {
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if !self.func.dfg.value_is_valid(val) {
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return err!(val, "Invalid value in {}", vreg);
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}
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if !self.func.dfg.value_is_attached(val) {
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return err!(val, "Detached value in {}", vreg);
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}
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if self.liveness.get(val).is_none() {
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return err!(val, "Value in {} has no live range", vreg);
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};
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// Check RPO ordering with the previous values in the virtual register.
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let def = self.func.dfg.value_def(val).into();
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let def_ebb = self.func.layout.pp_ebb(def);
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for &prev_val in &values[0..idx] {
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let prev_def = self.func.dfg.value_def(prev_val);
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// Enforce RPO of defs in the virtual register.
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match self.domtree.rpo_cmp(prev_def, def, &self.func.layout) {
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Ordering::Less => {}
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Ordering::Equal => {
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return err!(val, "Value in {} has same def as {}", vreg, prev_val);
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}
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Ordering::Greater => {
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return err!(val,
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"Value in {} in wrong order relative to {}",
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vreg,
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prev_val);
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}
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}
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// Knowing that values are in RPO order, we can check for interference this
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// way.
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if self.liveness[prev_val].overlaps_def(def, def_ebb, &self.func.layout) {
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return err!(val, "Value def in {} interferes with {}", vreg, prev_val);
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}
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}
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}
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}
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Ok(())
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}
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fn check_cssa(&self) -> Result {
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for ebb in self.func.layout.ebbs() {
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let ebb_args = self.func.dfg.ebb_args(ebb);
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for &(_, pred) in self.cfg.get_predecessors(ebb) {
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let pred_args = self.func.dfg.inst_variable_args(pred);
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// This should have been caught by an earlier verifier pass.
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assert_eq!(ebb_args.len(),
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pred_args.len(),
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"Wrong arguments on branch.");
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for (&ebb_arg, &pred_arg) in ebb_args.iter().zip(pred_args) {
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if !self.virtregs.same_class(ebb_arg, pred_arg) {
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return err!(pred,
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"{} and {} must be in the same virtual register",
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ebb_arg,
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pred_arg);
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}
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}
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}
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}
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Ok(())
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}
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}
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