1dddba649a
The x64 backend currently builds the `RealRegUniverse` in a way that is generating somewhat suboptimal code. In many blocks, we see uses of callee-save (non-volatile) registers (r12, r13, r14, rbx) first, even in very short leaf functions where there are plenty of volatiles to use. This is leading to unnecessary spills/reloads. On one (local) test program, a medium-sized C benchmark compiled to Wasm and run on Wasmtime, I am seeing a ~10% performance improvement with this change; it will be less pronounced in programs with high register pressure (there we are likely to use all registers regardless, so the prologue/epilogue will save/restore all callee-saves), or in programs with fewer calls, but this is a clear win for small functions and in many cases removes prologue/epilogue clobber-saves altogether. Separately, I think the RA's coalescing is tripping up a bit in some cases; see e.g. the filetest touched by this commit that loads a value into %rsi then moves to %rax and returns immediately. This is an orthogonal issue, though, and should be addressed (if worthwhile) in regalloc.rs.
62 lines
1.4 KiB
Plaintext
62 lines
1.4 KiB
Plaintext
test compile
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target x86_64
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feature "experimental_x64"
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function %add_from_mem_u32_1(i64, i32) -> i32 {
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block0(v0: i64, v1: i32):
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v2 = load.i32 v0
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v3 = iadd.i32 v2, v1
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; check: addl 0(%rdi), %esi
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return v3
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}
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function %add_from_mem_u32_2(i64, i32) -> i32 {
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block0(v0: i64, v1: i32):
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v2 = load.i32 v0
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v3 = iadd.i32 v1, v2
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; check: addl 0(%rdi), %esi
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return v3
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}
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function %add_from_mem_u64_1(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = load.i64 v0
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v3 = iadd.i64 v2, v1
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; check: addq 0(%rdi), %rsi
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return v3
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}
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function %add_from_mem_u64_2(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = load.i64 v0
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v3 = iadd.i64 v1, v2
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; check: addq 0(%rdi), %rsi
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return v3
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}
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; test narrow loads: 8-bit load should not merge because the `addl` is 32 bits
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; and would load 32 bits from memory, which may go beyond the end of the heap.
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function %add_from_mem_not_narrow(i64, i8) -> i8 {
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block0(v0: i64, v1: i8):
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v2 = load.i8 v0
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v3 = iadd.i8 v2, v1
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; check: movzbq 0(%rdi), %rdi
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; nextln: addl %esi, %edi
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return v3
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}
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function %no_merge_if_lookback_use(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = load.i64 v0
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v3 = iadd.i64 v2, v0
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store.i64 v3, v1
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v4 = load.i64 v3
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return v4
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; check: movq 0(%rdi), %rax
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; nextln: movq %rax, %rcx
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; nextln: addq %rdi, %rcx
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; nextln: movq %rcx, 0(%rsi)
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; nextln: movq 0(%rax,%rdi,1), %rsi
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; nextln: movq %rsi, %rax
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}
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