48573b52b2
I hadn't realized before that the filetest backend for `test vcode` is doing essentially what `compile` is doing, but for new (`MachInst`) backends: it is just getting a disassembly and running it through filecheck. There's no reason not to reuse `test compile` for the AArch64 tests as well. This was motivated by the desire to have "this IR compiles successfully" tests work on both x86 and AArch64. It seems this should work fine by adding multiple `target` directives when a test case should be compile-tested on multiple architectures.
159 lines
2.7 KiB
Plaintext
159 lines
2.7 KiB
Plaintext
test compile
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target aarch64
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function %f_u_8_64(i8) -> i64 {
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block0(v0: i8):
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v1 = uextend.i64 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxtb x0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f_u_8_32(i8) -> i32 {
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block0(v0: i8):
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v1 = uextend.i32 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxtb w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f_u_8_16(i8) -> i16 {
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block0(v0: i8):
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v1 = uextend.i16 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxtb w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f_s_8_64(i8) -> i64 {
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block0(v0: i8):
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v1 = sextend.i64 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtb x0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f_s_8_32(i8) -> i32 {
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block0(v0: i8):
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v1 = sextend.i32 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtb w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f_s_8_16(i8) -> i16 {
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block0(v0: i8):
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v1 = sextend.i16 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtb w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f_u_16_64(i16) -> i64 {
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block0(v0: i16):
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v1 = uextend.i64 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxth x0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f_u_16_32(i16) -> i32 {
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block0(v0: i16):
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v1 = uextend.i32 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: uxth w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f_s_16_64(i16) -> i64 {
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block0(v0: i16):
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v1 = sextend.i64 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxth x0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f_s_16_32(i16) -> i32 {
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block0(v0: i16):
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v1 = sextend.i32 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxth w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f_u_32_64(i32) -> i64 {
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block0(v0: i32):
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v1 = uextend.i64 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f_s_32_64(i32) -> i64 {
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block0(v0: i32):
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v1 = sextend.i64 v0
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtw x0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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