672e4abd7e
Ensure that the set of register classes is closed under intersection. Provide a RegClass::intersect() method which finds the register class representing the intersection of two classes. Generate a bit-mask of subclasses for each register class to be used by the intersect() method. Ensure that register classes are sorted topologically. This is also used by the intersect() method.
83 lines
2.5 KiB
Python
83 lines
2.5 KiB
Python
"""
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Generate register bank descriptions for each ISA.
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"""
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from __future__ import absolute_import
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import srcgen
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try:
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from typing import Sequence # noqa
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from cdsl.isa import TargetISA # noqa
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from cdsl.registers import RegBank, RegClass # noqa
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except ImportError:
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pass
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def gen_regbank(regbank, fmt):
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# type: (RegBank, srcgen.Formatter) -> None
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"""
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Emit a static data definition for regbank.
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"""
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with fmt.indented('RegBank {', '},'):
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fmt.line('name: "{}",'.format(regbank.name))
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fmt.line('first_unit: {},'.format(regbank.first_unit))
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fmt.line('units: {},'.format(regbank.units))
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fmt.line(
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'names: &[{}],'
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.format(', '.join('"{}"'.format(n) for n in regbank.names)))
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fmt.line('prefix: "{}",'.format(regbank.prefix))
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def gen_regclass(rc, fmt):
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# type: (RegClass, srcgen.Formatter) -> None
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"""
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Emit a static data definition for a register class.
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"""
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fmt.comment(rc.name)
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with fmt.indented('RegClassData {', '},'):
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fmt.line('index: {},'.format(rc.index))
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fmt.line('width: {},'.format(rc.width))
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fmt.line('subclasses: 0x{:x},'.format(rc.subclass_mask()))
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mask = ', '.join('0x{:08x}'.format(x) for x in rc.mask())
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fmt.line('mask: [{}],'.format(mask))
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def gen_isa(isa, fmt):
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# type: (TargetISA, srcgen.Formatter) -> None
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"""
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Generate register tables for isa.
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"""
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if not isa.regbanks:
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print('cargo:warning={} has no register banks'.format(isa.name))
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rcs = list() # type: List[RegClass]
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with fmt.indented('pub static INFO: RegInfo = RegInfo {', '};'):
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# Bank descriptors.
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with fmt.indented('banks: &[', '],'):
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for regbank in isa.regbanks:
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gen_regbank(regbank, fmt)
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rcs += regbank.classes
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fmt.line('classes: &CLASSES,')
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# Register class descriptors.
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with fmt.indented(
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'const CLASSES: [RegClassData; {}] = ['.format(len(rcs)), '];'):
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for idx, rc in enumerate(rcs):
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assert idx == rc.index
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gen_regclass(rc, fmt)
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# Emit constants referencing the register classes.
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for rc in rcs:
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fmt.line('#[allow(dead_code)]')
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fmt.line(
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'pub const {}: RegClass = &CLASSES[{}];'
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.format(rc.name, rc.index))
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def generate(isas, out_dir):
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# type: (Sequence[TargetISA], str) -> None
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for isa in isas:
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fmt = srcgen.Formatter()
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gen_isa(isa, fmt)
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fmt.update_file('registers-{}.rs'.format(isa.name), out_dir)
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