cdb3a71dd1
These instructions have a fixed register constraint; the shift amount is passed in CL. Add meta language syntax so a fixed register can be specified as "GPR.rcx".
39 lines
1.1 KiB
Plaintext
39 lines
1.1 KiB
Plaintext
; binary emission of 32-bit code.
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test binemit
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isa intel
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; The binary encodings can be verified with the command:
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;
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; sed -ne 's/^ *; asm: *//p' filetests/isa/intel/binary32.cton | llvm-mc -show-encoding -triple=i386
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;
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function I32() {
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ebb0:
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[-,%rcx] v1 = iconst.i32 1
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[-,%rsi] v2 = iconst.i32 2
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; Integer Register-Register Operations.
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; asm: addl %esi, %ecx
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[-,%rcx] v10 = iadd v1, v2 ; bin: 01 f1
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; asm: addl %ecx, %esi
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[-,%rsi] v11 = iadd v2, v1 ; bin: 01 ce
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; Dynamic shifts take the shift amount in %rcx.
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; asm: shll %cl, %esi
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[-,%rsi] v12 = ishl v2, v1 ; bin: d3 e6
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; asm: shll %cl, %ecx
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[-,%rcx] v13 = ishl v1, v1 ; bin: d3 e1
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; asm: shrl %cl, %esi
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[-,%rsi] v14 = ushr v2, v1 ; bin: d3 ee
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; asm: shrl %cl, %ecx
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[-,%rcx] v15 = ushr v1, v1 ; bin: d3 e9
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; asm: sarl %cl, %esi
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[-,%rsi] v16 = sshr v2, v1 ; bin: d3 fe
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; asm: sarl %cl, %ecx
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[-,%rcx] v17 = sshr v1, v1 ; bin: d3 f9
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return
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}
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