62cbb5045e
* riscv64: Swap order of `VecAluRRR` source registers
These were accidentally reversed from what we declare in the isle emit helper
* riscv64: Add SIMD `isub`
* riscv64: Add SIMD `imul`
* riscv64: Add `{u,s}mulhi`
* riscv64: Add `b{and,or,xor}`
* cranelift: Move `imul.i8x16` runtest to separate file
Looks like x86 does not implement it
* riscv64: Better formatting for `VecAluOpRRR`
* cranelift: Enable x86 SIMD tests with `has_sse41=false`
74 lines
1.3 KiB
Plaintext
74 lines
1.3 KiB
Plaintext
test compile precise-output
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set unwind_info=false
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target riscv64 has_v
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function %umulhi_i8x16(i8x16, i8x16) -> i8x16 {
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block0(v0: i8x16, v1: i8x16):
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v2 = umulhi v0, v1
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return v2
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}
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; VCode:
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; block0:
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; vmulhu.vv v10,v10,v11 #avl=16, #vtype=(e8, m1, ta, ma)
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; .byte 0x57, 0x70, 0x08, 0xcc
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; .byte 0x57, 0xa5, 0xa5, 0x92
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; ret
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function %umulhi_i16x8(i16x8, i16x8) -> i16x8 {
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block0(v0: i16x8, v1: i16x8):
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v2 = umulhi v0, v1
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return v2
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}
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; VCode:
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; block0:
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; vmulhu.vv v10,v10,v11 #avl=8, #vtype=(e16, m1, ta, ma)
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; .byte 0x57, 0x70, 0x84, 0xcc
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; .byte 0x57, 0xa5, 0xa5, 0x92
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; ret
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function %umulhi_i32x4(i32x4, i32x4) -> i32x4 {
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block0(v0: i32x4, v1: i32x4):
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v2 = umulhi v0, v1
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return v2
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}
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; VCode:
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; block0:
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; vmulhu.vv v10,v10,v11 #avl=4, #vtype=(e32, m1, ta, ma)
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; .byte 0x57, 0x70, 0x02, 0xcd
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; .byte 0x57, 0xa5, 0xa5, 0x92
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; ret
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function %umulhi_i64x2(i64x2, i64x2) -> i64x2 {
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block0(v0: i64x2, v1: i64x2):
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v2 = umulhi v0, v1
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return v2
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}
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; VCode:
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; block0:
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; vmulhu.vv v10,v10,v11 #avl=2, #vtype=(e64, m1, ta, ma)
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; .byte 0x57, 0x70, 0x81, 0xcd
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; .byte 0x57, 0xa5, 0xa5, 0x92
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; ret
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