62641d4553
The carry and borrow values are boolean, so we have to convert them to an integer type with bint(c) before we can add them to the result. Also tweak the default legalizer action for unsupported types: Only attempt a narrowing pattern for lane types > 32 bits. This was found by @angusholder's new type checks in the verifier.
144 lines
3.7 KiB
Python
144 lines
3.7 KiB
Python
"""
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Patterns for legalizing the `base` instruction set.
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The base Cretonne instruction set is 'fat', and many instructions don't have
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legal representations in a given target ISA. This module defines legalization
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patterns that describe how base instructions can be transformed to other base
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instructions that are legal.
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"""
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from __future__ import absolute_import
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from .instructions import iadd, iadd_cout, iadd_cin, iadd_carry, iadd_imm
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from .instructions import isub, isub_bin, isub_bout, isub_borrow
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from .instructions import band, bor, bxor, isplit, iconcat
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from .instructions import icmp, iconst, bint
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from cdsl.ast import Var
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from cdsl.xform import Rtl, XFormGroup
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narrow = XFormGroup('narrow', """
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Legalize instructions by narrowing.
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The transformations in the 'narrow' group work by expressing
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instructions in terms of smaller types. Operations on vector types are
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expressed in terms of vector types with fewer lanes, and integer
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operations are expressed in terms of smaller integer types.
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""")
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expand = XFormGroup('expand', """
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Legalize instructions by expansion.
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Rewrite instructions in terms of other instructions, generally
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operating on the same types as the original instructions.
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""")
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x = Var('x')
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y = Var('y')
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a = Var('a')
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a1 = Var('a1')
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a2 = Var('a2')
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b = Var('b')
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b1 = Var('b1')
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b2 = Var('b2')
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b_in = Var('b_in')
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b_int = Var('b_int')
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c = Var('c')
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c1 = Var('c1')
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c2 = Var('c2')
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c_in = Var('c_in')
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c_int = Var('c_int')
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xl = Var('xl')
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xh = Var('xh')
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yl = Var('yl')
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yh = Var('yh')
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al = Var('al')
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ah = Var('ah')
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narrow.legalize(
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a << iadd(x, y),
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Rtl(
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(xl, xh) << isplit(x),
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(yl, yh) << isplit(y),
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(al, c) << iadd_cout(xl, yl),
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ah << iadd_cin(xh, yh, c),
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a << iconcat(al, ah)
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))
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narrow.legalize(
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a << isub(x, y),
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Rtl(
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(xl, xh) << isplit(x),
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(yl, yh) << isplit(y),
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(al, b) << isub_bout(xl, yl),
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ah << isub_bin(xh, yh, b),
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a << iconcat(al, ah)
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))
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for bitop in [band, bor, bxor]:
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narrow.legalize(
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a << bitop(x, y),
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Rtl(
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(xl, xh) << isplit(x),
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(yl, yh) << isplit(y),
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al << bitop(xl, yl),
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ah << bitop(xh, yh),
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a << iconcat(al, ah)
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))
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# Expand integer operations with carry for RISC architectures that don't have
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# the flags.
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expand.legalize(
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(a, c) << iadd_cout(x, y),
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Rtl(
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a << iadd(x, y),
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c << icmp('IntCC::UnsignedLessThan', a, x)
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))
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expand.legalize(
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(a, b) << isub_bout(x, y),
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Rtl(
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a << isub(x, y),
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b << icmp('IntCC::UnsignedGreaterThan', a, x)
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))
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expand.legalize(
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a << iadd_cin(x, y, c),
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Rtl(
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a1 << iadd(x, y),
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c_int << bint(c),
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a << iadd(a1, c_int)
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))
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expand.legalize(
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a << isub_bin(x, y, b),
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Rtl(
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a1 << isub(x, y),
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b_int << bint(b),
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a << isub(a1, b_int)
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))
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expand.legalize(
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(a, c) << iadd_carry(x, y, c_in),
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Rtl(
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(a1, c1) << iadd_cout(x, y),
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c_int << bint(c_in),
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(a, c2) << iadd_cout(a1, c_int),
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c << bor(c1, c2)
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))
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expand.legalize(
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(a, b) << isub_borrow(x, y, b_in),
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Rtl(
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(a1, b1) << isub_bout(x, y),
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b_int << bint(b_in),
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(a, b2) << isub_bout(a1, b_int),
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b << bor(b1, b2)
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))
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# Expansions for immediates that are too large.
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expand.legalize(
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a << iadd_imm(x, y),
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Rtl(
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a1 << iconst(y),
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a << iadd(x, a1)
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))
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