470 lines
18 KiB
Rust
470 lines
18 KiB
Rust
//! This module exposes the machine-specific backend definition pieces.
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//!
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//! The MachInst infrastructure is the compiler backend, from CLIF
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//! (ir::Function) to machine code. The purpose of this infrastructure is, at a
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//! high level, to do instruction selection/lowering (to machine instructions),
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//! register allocation, and then perform all the fixups to branches, constant
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//! data references, etc., needed to actually generate machine code.
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//!
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//! The container for machine instructions, at various stages of construction,
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//! is the `VCode` struct. We refer to a sequence of machine instructions organized
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//! into basic blocks as "vcode". This is short for "virtual-register code", though
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//! it's a bit of a misnomer because near the end of the pipeline, vcode has all
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//! real registers. Nevertheless, the name is catchy and we like it.
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//!
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//! The compilation pipeline, from an `ir::Function` (already optimized as much as
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//! you like by machine-independent optimization passes) onward, is as follows.
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//! (N.B.: though we show the VCode separately at each stage, the passes
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//! mutate the VCode in place; these are not separate copies of the code.)
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//!
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//! ```plain
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//!
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//! ir::Function (SSA IR, machine-independent opcodes)
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//! |
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//! | [lower]
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//! |
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//! VCode<arch_backend::Inst> (machine instructions:
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//! | - mostly virtual registers.
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//! | - cond branches in two-target form.
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//! | - branch targets are block indices.
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//! | - in-memory constants held by insns,
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//! | with unknown offsets.
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//! | - critical edges (actually all edges)
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//! | are split.)
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//! | [regalloc]
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//! |
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//! VCode<arch_backend::Inst> (machine instructions:
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//! | - all real registers.
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//! | - new instruction sequence returned
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//! | out-of-band in RegAllocResult.
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//! | - instruction sequence has spills,
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//! | reloads, and moves inserted.
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//! | - other invariants same as above.)
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//! |
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//! | [preamble/postamble]
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//! |
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//! VCode<arch_backend::Inst> (machine instructions:
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//! | - stack-frame size known.
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//! | - out-of-band instruction sequence
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//! | has preamble prepended to entry
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//! | block, and postamble injected before
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//! | every return instruction.
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//! | - all symbolic stack references to
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//! | stackslots and spillslots are resolved
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//! | to concrete FP-offset mem addresses.)
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//! |
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//! | [binary emission via MachBuffer
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//! | with streaming branch resolution/simplification]
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//! |
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//! Vec<u8> (machine code!)
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//!
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//! ```
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use crate::binemit::{CodeInfo, CodeOffset, StackMap};
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use crate::ir::condcodes::IntCC;
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use crate::ir::{Function, SourceLoc, StackSlot, Type, ValueLabel};
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use crate::isa::unwind::input as unwind_input;
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use crate::result::CodegenResult;
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use crate::settings::Flags;
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use crate::value_label::ValueLabelsRanges;
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use alloc::boxed::Box;
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use alloc::vec::Vec;
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use core::fmt::Debug;
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use core::ops::Range;
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use cranelift_entity::PrimaryMap;
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use regalloc::RegUsageCollector;
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use regalloc::{
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RealReg, RealRegUniverse, Reg, RegClass, RegUsageMapper, SpillSlot, VirtualReg, Writable,
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};
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use smallvec::{smallvec, SmallVec};
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use std::hash::Hasher;
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use std::string::String;
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use target_lexicon::Triple;
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#[cfg(feature = "unwind")]
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use crate::isa::unwind::systemv::RegisterMappingError;
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pub mod lower;
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pub use lower::*;
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pub mod vcode;
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pub use vcode::*;
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pub mod compile;
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pub use compile::*;
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pub mod blockorder;
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pub use blockorder::*;
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pub mod abi;
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pub use abi::*;
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pub mod abi_impl;
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pub use abi_impl::*;
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pub mod buffer;
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pub use buffer::*;
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pub mod adapter;
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pub use adapter::*;
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pub mod helpers;
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pub use helpers::*;
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pub mod inst_common;
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pub use inst_common::*;
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pub mod valueregs;
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pub use valueregs::*;
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pub mod debug;
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/// A machine instruction.
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pub trait MachInst: Clone + Debug {
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/// Return the registers referenced by this machine instruction along with
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/// the modes of reference (use, def, modify).
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fn get_regs(&self, collector: &mut RegUsageCollector);
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/// Map virtual registers to physical registers using the given virt->phys
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/// maps corresponding to the program points prior to, and after, this instruction.
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fn map_regs<RUM: RegUsageMapper>(&mut self, maps: &RUM);
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/// If this is a simple move, return the (source, destination) tuple of registers.
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fn is_move(&self) -> Option<(Writable<Reg>, Reg)>;
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/// Is this a terminator (branch or ret)? If so, return its type
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/// (ret/uncond/cond) and target if applicable.
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fn is_term<'a>(&'a self) -> MachTerminator<'a>;
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/// Returns true if the instruction is an epilogue placeholder.
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fn is_epilogue_placeholder(&self) -> bool;
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/// Should this instruction be included in the clobber-set?
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fn is_included_in_clobbers(&self) -> bool {
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true
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}
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/// If this is a load or store to the stack, return that info.
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fn stack_op_info(&self) -> Option<MachInstStackOpInfo> {
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None
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}
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/// Generate a move.
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fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Self;
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/// Generate a constant into a reg.
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fn gen_constant<F: FnMut(Type) -> Writable<Reg>>(
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to_regs: ValueRegs<Writable<Reg>>,
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value: u128,
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ty: Type,
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alloc_tmp: F,
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) -> SmallVec<[Self; 4]>;
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/// Possibly operate on a value directly in a spill-slot rather than a
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/// register. Useful if the machine has register-memory instruction forms
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/// (e.g., add directly from or directly to memory), like x86.
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fn maybe_direct_reload(&self, reg: VirtualReg, slot: SpillSlot) -> Option<Self>;
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/// Determine register class(es) to store the given Cranelift type, and the
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/// Cranelift type actually stored in the underlying register(s). May return
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/// an error if the type isn't supported by this backend.
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///
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/// If the type requires multiple registers, then the list of registers is
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/// returned in little-endian order.
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///
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/// Note that the type actually stored in the register(s) may differ in the
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/// case that a value is split across registers: for example, on a 32-bit
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/// target, an I64 may be stored in two registers, each of which holds an
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/// I32. The actually-stored types are used only to inform the backend when
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/// generating spills and reloads for individual registers.
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fn rc_for_type(ty: Type) -> CodegenResult<(&'static [RegClass], &'static [Type])>;
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/// Generate a jump to another target. Used during lowering of
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/// control flow.
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fn gen_jump(target: MachLabel) -> Self;
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/// Generate a NOP. The `preferred_size` parameter allows the caller to
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/// request a NOP of that size, or as close to it as possible. The machine
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/// backend may return a NOP whose binary encoding is smaller than the
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/// preferred size, but must not return a NOP that is larger. However,
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/// the instruction must have a nonzero size if preferred_size is nonzero.
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fn gen_nop(preferred_size: usize) -> Self;
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/// Get the register universe for this backend.
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fn reg_universe(flags: &Flags) -> RealRegUniverse;
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/// Align a basic block offset (from start of function). By default, no
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/// alignment occurs.
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fn align_basic_block(offset: CodeOffset) -> CodeOffset {
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offset
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}
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/// What is the worst-case instruction size emitted by this instruction type?
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fn worst_case_size() -> CodeOffset;
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/// What is the register class used for reference types (GC-observable pointers)? Can
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/// be dependent on compilation flags.
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fn ref_type_regclass(_flags: &Flags) -> RegClass;
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/// Does this instruction define a ValueLabel? Returns the `Reg` whose value
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/// becomes the new value of the `ValueLabel` after this instruction.
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fn defines_value_label(&self) -> Option<(ValueLabel, Reg)> {
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None
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}
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/// Create a marker instruction that defines a value label.
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fn gen_value_label_marker(_label: ValueLabel, _reg: Reg) -> Self {
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Self::gen_nop(0)
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}
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/// A label-use kind: a type that describes the types of label references that
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/// can occur in an instruction.
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type LabelUse: MachInstLabelUse;
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}
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/// A descriptor of a label reference (use) in an instruction set.
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pub trait MachInstLabelUse: Clone + Copy + Debug + Eq {
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/// Required alignment for any veneer. Usually the required instruction
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/// alignment (e.g., 4 for a RISC with 32-bit instructions, or 1 for x86).
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const ALIGN: CodeOffset;
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/// What is the maximum PC-relative range (positive)? E.g., if `1024`, a
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/// label-reference fixup at offset `x` is valid if the label resolves to `x
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/// + 1024`.
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fn max_pos_range(self) -> CodeOffset;
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/// What is the maximum PC-relative range (negative)? This is the absolute
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/// value; i.e., if `1024`, then a label-reference fixup at offset `x` is
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/// valid if the label resolves to `x - 1024`.
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fn max_neg_range(self) -> CodeOffset;
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/// What is the size of code-buffer slice this label-use needs to patch in
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/// the label's value?
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fn patch_size(self) -> CodeOffset;
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/// Perform a code-patch, given the offset into the buffer of this label use
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/// and the offset into the buffer of the label's definition.
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/// It is guaranteed that, given `delta = offset - label_offset`, we will
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/// have `offset >= -self.max_neg_range()` and `offset <=
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/// self.max_pos_range()`.
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fn patch(self, buffer: &mut [u8], use_offset: CodeOffset, label_offset: CodeOffset);
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/// Can the label-use be patched to a veneer that supports a longer range?
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/// Usually valid for jumps (a short-range jump can jump to a longer-range
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/// jump), but not for e.g. constant pool references, because the constant
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/// load would require different code (one more level of indirection).
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fn supports_veneer(self) -> bool;
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/// How many bytes are needed for a veneer?
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fn veneer_size(self) -> CodeOffset;
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/// Generate a veneer. The given code-buffer slice is `self.veneer_size()`
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/// bytes long at offset `veneer_offset` in the buffer. The original
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/// label-use will be patched to refer to this veneer's offset. A new
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/// (offset, LabelUse) is returned that allows the veneer to use the actual
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/// label. For veneers to work properly, it is expected that the new veneer
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/// has a larger range; on most platforms this probably means either a
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/// "long-range jump" (e.g., on ARM, the 26-bit form), or if already at that
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/// stage, a jump that supports a full 32-bit range, for example.
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fn generate_veneer(self, buffer: &mut [u8], veneer_offset: CodeOffset) -> (CodeOffset, Self);
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}
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/// Describes a block terminator (not call) in the vcode, when its branches
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/// have not yet been finalized (so a branch may have two targets).
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#[derive(Clone, Debug, PartialEq, Eq)]
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pub enum MachTerminator<'a> {
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/// Not a terminator.
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None,
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/// A return instruction.
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Ret,
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/// An unconditional branch to another block.
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Uncond(MachLabel),
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/// A conditional branch to one of two other blocks.
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Cond(MachLabel, MachLabel),
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/// An indirect branch with known possible targets.
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Indirect(&'a [MachLabel]),
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}
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impl<'a> MachTerminator<'a> {
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/// Get the successor labels named in a `MachTerminator`.
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pub fn get_succs(&self) -> SmallVec<[MachLabel; 2]> {
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let mut ret = smallvec![];
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match self {
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&MachTerminator::Uncond(l) => {
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ret.push(l);
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}
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&MachTerminator::Cond(l1, l2) => {
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ret.push(l1);
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ret.push(l2);
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}
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&MachTerminator::Indirect(ls) => {
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ret.extend(ls.iter().cloned());
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}
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_ => {}
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}
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ret
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}
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/// Is this a terminator?
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pub fn is_term(&self) -> bool {
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match self {
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MachTerminator::None => false,
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_ => true,
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}
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}
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}
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/// A trait describing the ability to encode a MachInst into binary machine code.
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pub trait MachInstEmit: MachInst {
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/// Persistent state carried across `emit` invocations.
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type State: MachInstEmitState<Self>;
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/// Constant information used in `emit` invocations.
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type Info: MachInstEmitInfo;
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/// Unwind info generator.
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type UnwindInfo: UnwindInfoGenerator<Self>;
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/// Emit the instruction.
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fn emit(&self, code: &mut MachBuffer<Self>, info: &Self::Info, state: &mut Self::State);
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/// Pretty-print the instruction.
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fn pretty_print(&self, mb_rru: Option<&RealRegUniverse>, state: &mut Self::State) -> String;
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}
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/// Constant information used to emit an instruction.
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pub trait MachInstEmitInfo {
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/// Return the target-independent settings used for the compilation of this
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/// particular function.
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fn flags(&self) -> &Flags;
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}
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/// A trait describing the emission state carried between MachInsts when
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/// emitting a function body.
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pub trait MachInstEmitState<I: MachInst>: Default + Clone + Debug {
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/// Create a new emission state given the ABI object.
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fn new(abi: &dyn ABICallee<I = I>) -> Self;
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/// Update the emission state before emitting an instruction that is a
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/// safepoint.
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fn pre_safepoint(&mut self, _stack_map: StackMap) {}
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/// Update the emission state to indicate instructions are associated with a
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/// particular SourceLoc.
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fn pre_sourceloc(&mut self, _srcloc: SourceLoc) {}
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}
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/// The result of a `MachBackend::compile_function()` call. Contains machine
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/// code (as bytes) and a disassembly, if requested.
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pub struct MachCompileResult {
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/// Machine code.
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pub buffer: MachBufferFinalized,
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/// Size of stack frame, in bytes.
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pub frame_size: u32,
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/// Disassembly, if requested.
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pub disasm: Option<String>,
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/// Unwind info.
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pub unwind_info: Option<unwind_input::UnwindInfo<Reg>>,
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/// Debug info: value labels to registers/stackslots at code offsets.
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pub value_labels_ranges: ValueLabelsRanges,
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/// Debug info: stackslots to stack pointer offsets.
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pub stackslot_offsets: PrimaryMap<StackSlot, u32>,
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}
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impl MachCompileResult {
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/// Get a `CodeInfo` describing section sizes from this compilation result.
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pub fn code_info(&self) -> CodeInfo {
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let code_size = self.buffer.total_size();
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CodeInfo {
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code_size,
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jumptables_size: 0,
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rodata_size: 0,
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total_size: code_size,
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}
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}
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}
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/// Top-level machine backend trait, which wraps all monomorphized code and
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/// allows a virtual call from the machine-independent `Function::compile()`.
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pub trait MachBackend {
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/// Compile the given function.
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fn compile_function(
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&self,
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func: &Function,
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want_disasm: bool,
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) -> CodegenResult<MachCompileResult>;
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/// Return flags for this backend.
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fn flags(&self) -> &Flags;
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/// Hashes all flags, both ISA-independent and ISA-specific, into the
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/// specified hasher.
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fn hash_all_flags(&self, hasher: &mut dyn Hasher);
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/// Return triple for this backend.
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fn triple(&self) -> Triple;
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/// Return name for this backend.
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fn name(&self) -> &'static str;
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/// Return the register universe for this backend.
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fn reg_universe(&self) -> &RealRegUniverse;
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/// Machine-specific condcode info needed by TargetIsa.
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/// Condition that will be true when an IaddIfcout overflows.
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fn unsigned_add_overflow_condition(&self) -> IntCC;
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/// Machine-specific condcode info needed by TargetIsa.
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/// Condition that will be true when an IsubIfcout overflows.
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fn unsigned_sub_overflow_condition(&self) -> IntCC;
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/// Produces unwind info based on backend results.
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#[cfg(feature = "unwind")]
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fn emit_unwind_info(
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&self,
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_result: &MachCompileResult,
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_kind: UnwindInfoKind,
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) -> CodegenResult<Option<crate::isa::unwind::UnwindInfo>> {
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// By default, an backend cannot produce unwind info.
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Ok(None)
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}
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/// Creates a new System V Common Information Entry for the ISA.
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#[cfg(feature = "unwind")]
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fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
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// By default, an ISA cannot create a System V CIE
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None
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}
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/// Maps a regalloc::Reg to a DWARF register number.
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#[cfg(feature = "unwind")]
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fn map_reg_to_dwarf(&self, _: Reg) -> Result<u16, RegisterMappingError> {
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Err(RegisterMappingError::UnsupportedArchitecture)
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}
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}
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/// Expected unwind info type.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[non_exhaustive]
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pub enum UnwindInfoKind {
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/// No unwind info.
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None,
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/// SystemV CIE/FDE unwind info.
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#[cfg(feature = "unwind")]
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SystemV,
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/// Windows X64 Unwind info
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#[cfg(feature = "unwind")]
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Windows,
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}
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/// Input data for UnwindInfoGenerator.
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pub struct UnwindInfoContext<'a, Inst: MachInstEmit> {
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/// Function instructions.
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pub insts: &'a [Inst],
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/// Instruction layout: end offsets
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pub insts_layout: &'a [CodeOffset],
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/// Length of the function.
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pub len: CodeOffset,
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/// Prologue range.
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pub prologue: Range<u32>,
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/// Epilogue ranges.
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pub epilogues: &'a [Range<u32>],
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}
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/// UnwindInfo generator/helper.
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pub trait UnwindInfoGenerator<I: MachInstEmit> {
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/// Creates unwind info based on function signature and
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/// emitted instructions.
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fn create_unwind_info(
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context: UnwindInfoContext<I>,
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) -> CodegenResult<Option<unwind_input::UnwindInfo<Reg>>>;
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}
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/// Info about an operation that loads or stores from/to the stack.
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#[derive(Clone, Copy, Debug)]
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pub enum MachInstStackOpInfo {
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/// Load from an offset from the nominal stack pointer into the given reg.
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LoadNomSPOff(Reg, i64),
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/// Store to an offset from the nominal stack pointer from the given reg.
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StoreNomSPOff(Reg, i64),
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/// Adjustment of nominal-SP up or down. This value is added to subsequent
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/// offsets in loads/stores above to produce real-SP offsets.
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NomSPAdj(i64),
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}
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