89b5fc776d
This adds support for the IBM z/Architecture (s390x-ibm-linux). The status of the s390x backend in its current form is: - Wasmtime is fully functional and passes all tests on s390x. - All back-end features supported, with the exception of SIMD. - There is still a lot of potential for performance improvements. - Currently the only supported processor type is z15.
356 lines
6.3 KiB
Plaintext
356 lines
6.3 KiB
Plaintext
test compile
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set avoid_div_traps=1
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target s390x
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; SDIV
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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function %sdiv_i64(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = sdiv.i64 v0, v1
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return v2
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}
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; check: lgr %r1, %r2
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; nextln: cgite %r3, 0
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; nextln: llihf %r2, 2147483647
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; nextln: iilf %r2, 4294967295
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; nextln: xgr %r2, %r1
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; nextln: ngr %r2, %r3
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; nextln: cgite %r2, -1
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; nextln: dsgr %r0, %r3
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; nextln: lgr %r2, %r1
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; nextln: br %r14
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function %sdiv_i64_imm(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 2
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v2 = sdiv.i64 v0, v1
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return v2
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}
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; check: lgr %r1, %r2
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; nextln: lghi %r2, 2
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; nextln: dsgr %r0, %r2
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; nextln: lgr %r2, %r1
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; nextln: br %r14
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function %sdiv_i32(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = sdiv.i32 v0, v1
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return v2
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}
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; check: lgfr %r1, %r2
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; nextln: cite %r3, 0
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; nextln: iilf %r2, 2147483647
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; nextln: xr %r2, %r1
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; nextln: nr %r2, %r3
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; nextln: cite %r2, -1
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; nextln: dsgfr %r0, %r3
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; nextln: lr %r2, %r1
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; nextln: br %r14
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function %sdiv_i32_imm(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = sdiv.i32 v0, v1
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return v2
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}
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; check: lgfr %r1, %r2
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; nextln: lhi %r2, 2
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; nextln: dsgfr %r0, %r2
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; nextln: lr %r2, %r1
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; nextln: br %r14
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function %sdiv_i16(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = sdiv.i16 v0, v1
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return v2
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}
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; check: lghr %r1, %r2
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; nextln: lhr %r2, %r3
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; nextln: cite %r2, 0
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; nextln: lhi %r3, 32767
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; nextln: xr %r3, %r1
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; nextln: nr %r3, %r2
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; nextln: cite %r3, -1
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; nextln: dsgfr %r0, %r2
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; nextln: lr %r2, %r1
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; nextln: br %r14
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function %sdiv_i16_imm(i16) -> i16 {
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block0(v0: i16):
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v1 = iconst.i16 2
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v2 = sdiv.i16 v0, v1
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return v2
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}
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; check: lghr %r1, %r2
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; nextln: lhi %r2, 2
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; nextln: dsgfr %r0, %r2
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; nextln: lr %r2, %r1
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; nextln: br %r14
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function %sdiv_i8(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = sdiv.i8 v0, v1
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return v2
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}
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; check: lgbr %r1, %r2
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; nextln: lbr %r2, %r3
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; nextln: cite %r2, 0
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; nextln: lhi %r3, 127
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; nextln: xr %r3, %r1
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; nextln: nr %r3, %r2
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; nextln: cite %r3, -1
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; nextln: dsgfr %r0, %r2
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; nextln: lr %r2, %r1
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; nextln: br %r14
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function %sdiv_i8_imm(i8) -> i8 {
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block0(v0: i8):
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v1 = iconst.i8 2
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v2 = sdiv.i8 v0, v1
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return v2
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}
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; check: lgbr %r1, %r2
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; nextln: lhi %r2, 2
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; nextln: dsgfr %r0, %r2
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; nextln: lr %r2, %r1
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; nextln: br %r14
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; UDIV
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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function %udiv_i64(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = udiv.i64 v0, v1
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return v2
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}
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; check: lghi %r0, 0
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; nextln: lgr %r1, %r2
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; nextln: cgite %r3, 0
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; nextln: dlgr %r0, %r3
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; nextln: lgr %r2, %r1
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; nextln: br %r14
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function %udiv_i64_imm(i64) -> i64 {
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block0(v0: i64):
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v1 = iconst.i64 2
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v2 = udiv.i64 v0, v1
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return v2
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}
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; check: lghi %r0, 0
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; nextln: lgr %r1, %r2
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; nextln: lghi %r2, 2
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; nextln: dlgr %r0, %r2
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; nextln: lgr %r2, %r1
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; nextln: br %r14
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function %udiv_i32(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = udiv.i32 v0, v1
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return v2
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}
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; check: lhi %r0, 0
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; nextln: lr %r1, %r2
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; nextln: cite %r3, 0
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; nextln: dlr %r0, %r3
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; nextln: lr %r2, %r1
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; nextln: br %r14
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function %udiv_i32_imm(i32) -> i32 {
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block0(v0: i32):
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v1 = iconst.i32 2
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v2 = udiv.i32 v0, v1
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return v2
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}
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; check: lhi %r0, 0
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; nextln: lr %r1, %r2
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; nextln: lhi %r2, 2
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; nextln: dlr %r0, %r2
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; nextln: lr %r2, %r1
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; nextln: br %r14
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function %udiv_i16(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = udiv.i16 v0, v1
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return v2
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}
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; check: lhi %r0, 0
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; nextln: llhr %r1, %r2
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; nextln: llhr %r2, %r3
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; nextln: cite %r2, 0
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; nextln: dlr %r0, %r2
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; nextln: lr %r2, %r1
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; nextln: br %r14
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function %udiv_i16_imm(i16) -> i16 {
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block0(v0: i16):
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v1 = iconst.i16 2
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v2 = udiv.i16 v0, v1
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return v2
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}
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; check: lhi %r0, 0
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; nextln: llhr %r1, %r2
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; nextln: lhi %r2, 2
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; nextln: dlr %r0, %r2
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; nextln: lr %r2, %r1
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; nextln: br %r14
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function %udiv_i8(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = udiv.i8 v0, v1
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return v2
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}
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; check: lhi %r0, 0
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; nextln: llcr %r1, %r2
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; nextln: llcr %r2, %r3
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; nextln: cite %r2, 0
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; nextln: dlr %r0, %r2
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; nextln: lr %r2, %r1
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; nextln: br %r14
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function %udiv_i8_imm(i8) -> i8 {
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block0(v0: i8):
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v1 = iconst.i8 2
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v2 = udiv.i8 v0, v1
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return v2
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}
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; check: lhi %r0, 0
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; nextln: llcr %r1, %r2
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; nextln: lhi %r2, 2
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; nextln: dlr %r0, %r2
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; nextln: lr %r2, %r1
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; nextln: br %r14
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; SREM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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function %srem_i64(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = srem.i64 v0, v1
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return v2
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}
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; check: lgr %r1, %r2
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; nextln: cgite %r3, 0
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; nextln: cghi %r3, -1
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; nextln: locghie %r1, 0
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; nextln: dsgr %r0, %r3
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; nextln: lgr %r2, %r0
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; nextln: br %r14
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function %srem_i32(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = srem.i32 v0, v1
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return v2
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}
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; check: lgfr %r1, %r2
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; nextln: cite %r3, 0
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; nextln: dsgfr %r0, %r3
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; nextln: lr %r2, %r0
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; nextln: br %r14
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function %srem_i16(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = srem.i16 v0, v1
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return v2
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}
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; check: lghr %r1, %r2
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; nextln: lhr %r2, %r3
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; nextln: cite %r2, 0
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; nextln: dsgfr %r0, %r2
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; nextln: lr %r2, %r0
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; nextln: br %r14
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function %srem_i8(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = srem.i8 v0, v1
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return v2
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}
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; check: lgbr %r1, %r2
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; nextln: lbr %r2, %r3
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; nextln: cite %r2, 0
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; nextln: dsgfr %r0, %r2
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; nextln: lr %r2, %r0
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; nextln: br %r14
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;; UREM
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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function %urem_i64(i64, i64) -> i64 {
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block0(v0: i64, v1: i64):
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v2 = urem.i64 v0, v1
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return v2
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}
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; check: lghi %r0, 0
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; nextln: lgr %r1, %r2
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; nextln: cgite %r3, 0
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; nextln: dlgr %r0, %r3
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; nextln: lgr %r2, %r0
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; nextln: br %r14
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function %urem_i32(i32, i32) -> i32 {
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block0(v0: i32, v1: i32):
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v2 = urem.i32 v0, v1
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return v2
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}
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; check: lhi %r0, 0
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; nextln: lr %r1, %r2
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; nextln: cite %r3, 0
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; nextln: dlr %r0, %r3
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; nextln: lr %r2, %r0
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; nextln: br %r14
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function %urem_i16(i16, i16) -> i16 {
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block0(v0: i16, v1: i16):
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v2 = urem.i16 v0, v1
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return v2
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}
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; check: lhi %r0, 0
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; nextln: llhr %r1, %r2
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; nextln: llhr %r2, %r3
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; nextln: cite %r2, 0
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; nextln: dlr %r0, %r2
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; nextln: lr %r2, %r0
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; nextln: br %r14
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function %urem_i8(i8, i8) -> i8 {
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block0(v0: i8, v1: i8):
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v2 = urem.i8 v0, v1
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return v2
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}
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; check: lhi %r0, 0
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; nextln: llcr %r1, %r2
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; nextln: llcr %r2, %r3
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; nextln: cite %r2, 0
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; nextln: dlr %r0, %r2
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; nextln: lr %r2, %r0
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; nextln: br %r14
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