5fa0be3515
When storing an argument to a stack location for consumption by a callee, or storing a return value to an on-stack return slot for consumption by the caller, the ABI implementation was properly extending the value but was then performing a store with only the original width. This fixes the issue by always performing a 64-bit store of the extended value. Issue reported by @uweigand (thanks!).
133 lines
2.7 KiB
Plaintext
133 lines
2.7 KiB
Plaintext
test compile
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target aarch64
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function %f1(i64) -> i64 {
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fn0 = %g(i64) -> i64
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block0(v0: i64):
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v1 = call fn0(v0)
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: ldr x16, 8 ; b 12 ; data
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; nextln: blr x16
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f2(i32) -> i64 {
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fn0 = %g(i32 uext) -> i64
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block0(v0: i32):
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v1 = call fn0(v0)
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov w0, w0
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; nextln: ldr x16, 8 ; b 12 ; data
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; nextln: blr x16
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f3(i32) -> i32 uext {
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block0(v0: i32):
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return v0
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov w0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f4(i32) -> i64 {
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fn0 = %g(i32 sext) -> i64
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block0(v0: i32):
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v1 = call fn0(v0)
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return v1
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtw x0, w0
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; nextln: ldr x16, 8 ; b 12 ; data
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; nextln: blr x16
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f5(i32) -> i32 sext {
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block0(v0: i32):
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return v0
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: sxtw x0, w0
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f6(i8) -> i64 {
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fn0 = %g(i32, i32, i32, i32, i32, i32, i32, i32, i8 sext) -> i64
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block0(v0: i8):
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v1 = iconst.i32 42
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v2 = call fn0(v1, v1, v1, v1, v1, v1, v1, v1, v0)
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return v2
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x8, x0
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; nextln: sub sp, sp, #16
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; nextln: virtual_sp_offset_adjust 16
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; nextln: movz x0, #42
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; nextln: movz x1, #42
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; nextln: movz x2, #42
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; nextln: movz x3, #42
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; nextln: movz x4, #42
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; nextln: movz x5, #42
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; nextln: movz x6, #42
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; nextln: movz x7, #42
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; nextln: sxtb x8, w8
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; nextln: stur x8, [sp]
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; nextln: ldr x16, 8 ; b 12 ; data
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; nextln: blr x16
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; nextln: add sp, sp, #16
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; nextln: virtual_sp_offset_adjust -16
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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function %f7(i8) -> i32, i32, i32, i32, i32, i32, i32, i32, i8 sext {
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block0(v0: i8):
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v1 = iconst.i32 42
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return v1, v1, v1, v1, v1, v1, v1, v1, v0
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}
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; check: stp fp, lr, [sp, #-16]!
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; nextln: mov fp, sp
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; nextln: mov x9, x0
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; nextln: mov x8, x1
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; nextln: movz x0, #42
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; nextln: movz x1, #42
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; nextln: movz x2, #42
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; nextln: movz x3, #42
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; nextln: movz x4, #42
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; nextln: movz x5, #42
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; nextln: movz x6, #42
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; nextln: movz x7, #42
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; nextln: sxtb x9, w9
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; nextln: stur x9, [x8]
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; nextln: mov sp, fp
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; nextln: ldp fp, lr, [sp], #16
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; nextln: ret
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