5d8dd648d7
* x64: port scalar `fcmp` to ISLE Implement the CLIF lowering for the `fcmp` to ISLE. This adds a new type-matcher, `ty_scalar_float`, for detecting uses of `F32` and `F64`. * isle: rename `vec128` to `ty_vec12` This refactoring changes the name of the `vec128` matcher function to follow the `ty_*` convention of the other type matchers. It also makes the helper an inline function call. * x64: port vector `fcmp` to ISLE
66 lines
1.6 KiB
Plaintext
66 lines
1.6 KiB
Plaintext
test compile precise-output
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target x86_64
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function %f0(i64, i64) -> i64, i64 {
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block0(v0: i64, v1: i64):
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v2 = load.i64 v1
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v3 = icmp eq v0, v2
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v4 = bint.i64 v3
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v5 = select.i64 v3, v0, v1
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return v4, v5
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 13)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: movq 0(%rsi), %rax
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; Inst 3: cmpq %rax, %rdi
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; Inst 4: setz %cl
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; Inst 5: andq $1, %rcx
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; Inst 6: cmpq %rax, %rdi
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; Inst 7: cmovzq %rdi, %rsi
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; Inst 8: movq %rcx, %rax
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; Inst 9: movq %rsi, %rdx
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; Inst 10: movq %rbp, %rsp
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; Inst 11: popq %rbp
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; Inst 12: ret
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; }}
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function %f1(f64, i64) -> i64, f64 {
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block0(v0: f64, v1: i64):
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v2 = load.f64 v1
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v3 = fcmp eq v0, v2
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v4 = bint.i64 v3
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v5 = select.f64 v3, v0, v0
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return v4, v5
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}
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; VCode_ShowWithRRU {{
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; Entry block: 0
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; Block 0:
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; (original IR block: block0)
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; (instruction range: 0 .. 17)
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; Inst 0: pushq %rbp
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; Inst 1: movq %rsp, %rbp
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; Inst 2: movsd 0(%rdi), %xmm1
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; Inst 3: ucomisd %xmm1, %xmm0
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; Inst 4: setnp %sil
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; Inst 5: setz %dil
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; Inst 6: andl %edi, %esi
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; Inst 7: andq $1, %rsi
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; Inst 8: ucomisd %xmm0, %xmm1
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; Inst 9: movaps %xmm0, %xmm1
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; Inst 10: jz $next; movsd %xmm0, %xmm1; $next:
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; Inst 11: jnp $next; movsd %xmm0, %xmm1; $next:
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; Inst 12: movq %rsi, %rax
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; Inst 13: movaps %xmm1, %xmm0
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; Inst 14: movq %rbp, %rsp
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; Inst 15: popq %rbp
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; Inst 16: ret
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; }}
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