4e67e08efd
This switches from a custom list of architectures to use the target-lexicon crate. - "set is_64bit=1; isa x86" is replaced with "target x86_64", and similar for other architectures, and the `is_64bit` flag is removed entirely. - The `is_compressed` flag is removed too; it's no longer being used to control REX prefixes on x86-64, ARM and Thumb are separate architectures in target-lexicon, and we can figure out how to select RISC-V compressed encodings when we're ready.
27 lines
710 B
Plaintext
27 lines
710 B
Plaintext
; Test basic code generation for f32 memory WebAssembly instructions.
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test compile
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; We only test on 64-bit since the heap_addr instructions and vmctx parameters
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; explicitly mention the pointer width.
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target x86_64 haswell
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function %f32_load(i32, i64 vmctx) -> f32 {
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gv0 = vmctx
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heap0 = static gv0, min 0x0001_0000, bound 0x0001_0000_0000, guard 0x8000_0000
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ebb0(v0: i32, v1: i64):
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v2 = heap_addr.i64 heap0, v0, 1
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v3 = load.f32 v2
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return v3
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}
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function %f32_store(f32, i32, i64 vmctx) {
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gv0 = vmctx
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heap0 = static gv0, min 0x0001_0000, bound 0x0001_0000_0000, guard 0x8000_0000
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ebb0(v0: f32, v1: i32, v2: i64):
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v3 = heap_addr.i64 heap0, v1, 1
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store v0, v3
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return
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}
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